BQ28Z560-R1 Datasheet, PDF (51/60 Pages) Texas Instruments – Single Cell Li-Ion Battery Gas Gauge and Protection

bq28z560-R1
www.ti.com
SLUSBD3 – APRIL 2013
HDQ serial communication is normally initiated by the host processor sending a break command to the
bq28z560-R1. A break is detected when the DATA pin is driven to a logic-low state for a time t_(B) or greater. The
DATA pin should then be returned to its normal ready high logic state for a time t_(BR). The bq28z560-R1 is now
ready to receive information from the host processor.
The bq28z560-R1 is shipped in the I²C mode. TI provides tools to enable the HDQ peripheral.
HDQ HOST INTERRUPTION FEATURE
The default bq28z560-R1 behaves as an HDQ slave only device. If the HDQ interrupt function is enabled, the
bq28z560-R1 is capable of mastering and also communicating to a HDQ device. There is no mechanism for
negotiating who is to function as the HDQ master and care must be taken to avoid message collisions. The
interrupt is signaled to the host processor with the bq28z560-R1 mastering an HDQ "message." This message is
a fixed message that will be used to signal the interrupt condition. The message itself is 0x80 (slave write to
register 0x00) with no data byte being sent as the command is not intended to convey any status of the interrupt
condition. The HDQ interrupt function is not public and needs to be enabled by command.
When the SET_HDQINTEN subcommand is received, the bq28z560-R1 will detect any of the interrupt conditions
and assert the interrupt at 1-s intervals until the CLEAR_HDQINTEN command is received or the count of
HDQHostIntrTries has lapsed.
The number of tries for interrupting the host will be determined by the data flash parameter named
Configuration.Register.HDQHostIntrTries.
The HDQ host interrupt is triggered by the settings in the bat alert feature. The HDQ host interrupt signal will be
asserted when the Flags()[ALRT] bit is triggered, based on the settings in the BatAlertConfig() register.
I²C INTERFACE
The gas gauge supports the standard I²C read, incremental read, 1-byte write quick read, and functions. The 7-
bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as 1010101. The 8-bit
device address is therefore 0xAA or 0xAB for write or read, respectively.
Host Generated
Fuel Gauge Generated
S ADDR[6:0] 0 A CMD[7:0]
A DATA[7:0]
(a)
AP
S ADDR[6:0] 1 A DATA[7:0] N P
(b)
S ADDR[6:0] 0 A CMD[7:0]
A Sr ADDR[6:0]
(c)
1A
DATA[7:0]
NP
S ADDR[6:0] 0 A CMD[7:0]
A Sr ADDR[6:0]
(d)
1A
DATA[7:0]
A . . . DATA[7:0] N P
Figure 9. Supported I²C formats: (a) 1-byte write, (b) quick read, ©) 1 byte-read, and (d) incremental read
(S = Start, Sr = Repeated Start, A = Acknowledge, N = No Acknowledge, and P = Stop).
The "quick read" returns data at the address indicated by the address pointer. The address pointer, a register
internal to the I²C communication engine, increments whenever data is acknowledged by the bq28z560-R1 or
the I²C master. "Quick writes" function in the same manner and are a convenient means of sending multiple
bytes to consecutive command locations (such as 2-byte commands that require two bytes of data).
Attempt to write a read-only address (NACK after data sent by master):
S ADDR[6:0] 0 A CMD[7:0]
A DATA[7:0]
AP
Attempt to read an address above 0x7F (NACK command):
S
ADDR[6:0]
0 A CMD[7:0] N P
Attempt at incremental writes (NACK all extra data bytes sent):
S ADDR[6:0] 0 A CMD[7:0] A DATA[7:0]
A DATA[7:0] N _{. . .} N P
Copyright © 2013, Texas Instruments Incorporated
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