BQ28Z560-R1 Datasheet, PDF (2/60 Pages) Texas Instruments – Single Cell Li-Ion Battery Gas Gauge and Protection

bq28z560-R1
SLUSBD3 – APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
T_A
–40°C to 85°C
ORDERING INFORMATION⁽¹⁾
PART NUMBER
PACKAGE
bq28z560-R1DRZR
bq28z560-R1DRZT
12-pin, 2.5-mm × 4.0-mm
SON
TAPE AND REEL QUANTITY
3000
250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder on ti.com (www.ti.com).
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
θ_JA
θ_JC(top)
θ_JB
ψ_JT
ψ_JB
θ_JC(bottom)
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case(top) thermal resistance ⁽³⁾
Junction-to-board thermal resistance ⁽⁴⁾
Junction-to-top characterization parameter ⁽⁵⁾
Junction-to-board characterization parameter ⁽⁶⁾
Junction-to-case(bottom) thermal resistance ⁽⁷⁾
bq28z560-R1
SON
12 PINS
186.4
90.4
110.7
96.7
90
n/a
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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