BQ28Z560-R1 Datasheet, PDF (37/60 Pages) Texas Instruments – Single Cell Li-Ion Battery Gas Gauge and Protection

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bq28z560-R1
SLUSBD3 – APRIL 2013
RESCAP = No-load rate of compensation is applied to the reserve capacity calculation. True when set. Default is 0.
CalEn = bq28z560-R1 CALIBRATION mode is enabled. Default is 0.
RSVD = Reserved. Default = 0
RSVD = Reserved. Default = 0.
RSVD = Reserved. Default = 0.
GNDSEL = The ADC ground select control. The V_SS (Pin 6) is selected as ground reference when the bit is clear. Pin 7 is
selected when the bit is set. Default is 0.
IWAKE/RSNS1/RSNS0 = These bits configure the current wake function. Default is 0/0/1.
GNDSEL = The ADC ground select control. The V_SS (Pin 6) is selected as ground reference when the bit is clear. Pin 7 is
selected when the bit is set. Default is 0.
ResFactStep = Enables Ra step up/down to Max/Min Res Factor before disabling Ra updates. Default is 1.
SLEEP = The gas gauge can enter sleep, if operating conditions allow. True when set. Default is 1.
RMFCC = RM is updated with the value from FCC, on valid charge termination. True when set. Default is 1.
CLR_READ = Clear on Read the Fault Flag register. True when set. Default = 0.
ALRT_POL = Set polarity of Alert output. Set to 1 means active high, so any faults detected will change output from low to
high. Default = 0, which means any fault detected will change output from high to low.
RSVD = Reserved. Default = 0.
TEMPS = Selects external thermistor for Temperature() measurements. True when set. Default is 1.
Pack Configuration B Register
Some bq28z560-R1 pins are configured via the Pack Configuration B data flash register, as indicated in
Table 16. This register is programmed/read via the methods described in ACCESSING THE DATA FLASH. The
register is located at subclass = 64, offset = 2.
Bit 7
ChgDoDEoC
Bit 6
SE_TDD
Table 16. Pack Configuration B Bit Definition
Bit 5
VconsEN
Bit 4
SE_ISD
Bit 3
JEITA
Bit 2
LFPRelax
Bit 1
DoDWT
Bit 0
FConvEn
ChgDoDEoC = Enable DoD at EoC during charging only. True when set. Default is 1. Default setting is recommended.
SE_TDD = Enable Tab Disconnection Detection. True when set. Default is 1.
VconsEN = Enable voltage consistency check. True when set. Default is 1. Default setting is recommended.
SE_ISD = Enable Internal Short Detection. True when set. Default is 1.
JEITA = Enable JEITA Temperature Charging function. True when set. Default is 1.
LFPRelax = Enable LiFePO4 long RELAX mode when chemical ID 400 series is selected. True when set. Default is 1.
DoDWT = Enable Dod weighting for LiFePO4 support when chemical ID 400 series is selected. True when set. Default is
1.
FConvEn = Enable fast convergence algorithm. Default is 1. Default setting is recommended.
Pack Configuration C Register
Some bq28z560-R1 algorithm settings are configured via the Pack Configuration C data flash register, as
indicated in Table 17. This register is programmed/read via the methods described in ACCESSING THE DATA
FLASH. The register is located at subclass = 64, offset = 3.
Bit 7
RSVD
Bit 6
RSVDSBS
Table 17. Pack Configuration C Bit Definition
Bit 5
PIN12F1
Bit 4
PIN12F0
Bit 3
Bit 2
SleepWakeChg ChgFetTerm
Bit 1
CFET_INIT
Bit 0
DFET_INIT
RSVD = Reserved. Default = 0.
RSVDSBS = Reserved for SBS command set. True when set. Default is 0.
PIN12F1 = In combination with PIN12F0 will set the operation mode of pin 12 (see below).
PIN12F0 = In combination with PIN12F1 will set the operation mode of pin 12 (see below).
Copyright © 2013, Texas Instruments Incorporated
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