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TCA9554_15 Datasheet, PDF (5/38 Pages) Texas Instruments – TCA9554 Low Voltage 8-Bit I2C and SMBus Low-Power I/O Expander With Interrupt Output and Configuration Registers
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TCA9554
SCPS233D – MARCH 2012 – REVISED AUGUST 2015
6.4 Thermal Information
THERMAL METRIC(1)
TCA9554
PW (TSSOP) DBQ (SSOP) DB (SSOP)
UNIT
16 PINS
16 PINS
16 PINS
RθJA
RθJC(top)
RθJB
ψJT
ψJB
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
122.0
56.4
67.1
10.8
66.5
121.7
72.9
64.2
24.4
63.8
113.2
63.6
64.0
21.2
63.4
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VPORR
VPORF
Input diode clamp voltage
Power-on reset voltage, VCC rising
Power-on reset voltage, VCC falling
II = –18 mA
VI = VCC or GND, IO = 0
VI = VCC or GND, IO = 0
VOH
P-port high-level output voltage(2)
SDA (3)
IOH = –8 mA
IOH = –10 mA
VOL = 0.4 V
IOL
P port(4)
INT (5)
SCL, SDA
II
A0, A1, A2
IIH
P port
IIL
P port
VOL = 0.5 V
VOL = 0.7 V
VOL = 0.4 V
VI = VCC or GND
VI = VCC
VI = GND
VCC
1.65 V to 5.5 V
1.65 V
2.3 V
3V
4.5 V
1.65 V
2.3 V
3V
4.5 V
1.65 V to 5.5 V
1.65 V
2.3 V
3V
4.5 V
1.65 V
2.3 V
3V
4.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
MIN
TYP(1) MAX UNIT
–1.2
V
1.2
1.5
V
0.75
1.0
V
1.2
1.8
2.6
4.1
1.1
V
1.7
2.5
4.0
3
11
8
10
8
13
8
15
8
17
mA
10
14
10
17
10
20
10
24
3
7
±1
µA
±1
1 µA
–100 µA
(1) All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
(2) Each P-port I/O configured as a high output must be externally limited to a maximum of 10 mA, and the total current sourced by all I/Os
(P-ports P7-P0) through VCC should be limited to a maximum current of 80 mA.
(3) The SDA pin must be externally limited to a maximum of 12 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA)
through GND should be limited to a maximum current of 200 mA.
(4) Each P-port I/O configured as a low output must be externally limited to a maximum of 25 mA, and the total current sunk by all I/Os (P-
ports P7-P0, INT, and SDA) through GND should be limited to a maximum current of 200 mA.
(5) The INT pin must be externally limited to a maximum of 7 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA)
through GND should be limited to a maximum current of 200 mA.
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