TCA9554_15 Datasheet, PDF (21/38 Pages) Texas Instruments – TCA9554 Low Voltage 8-Bit I2C and SMBus Low-Power I/O Expander With Interrupt Output and Configuration Registers

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TCA9554
SCPS233D – MARCH 2012 – REVISED AUGUST 2015
8.6.3.1.2 Reads
The bus master first must send the TCA9554 address with the LSB set to a logic 0 (see Figure 18 for device
address). The command byte is sent after the address and determines which register is accessed. After a restart,
the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the
command byte then is sent by the TCA9554 (see Figure 22 and Figure 23). After a restart, the value of the
register defined by the command byte matches the register being accessed when the restart occurred. Data is
clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data
bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
Slave Address
ACK From
Slave
ACK From
Slave
Slave Address
ACK From
ACK From
Slave ^{Data From Register Master}
S 0 1 0 0 A2 A1 A0 0 A
Command Byte
A S 0 1 0 0 A2 A1 A0 1 A
Data
A
R/W
R/W
SCL
SDA
Read From
Port
Data Into
Port
Figure 22. Read From Register
NACK From
Data From Register _Master
Data
Last Byte
NA P
12 345678 9
Slave Address
Data From Port
S 0 1 0 0 A2 A1 A0 1 A
Data 1
Start
Condition
R/W
ACK From
Slave
Data From Port
A
Data 4
NA P
ACK From
Master
NACK From
Master
Stop
Condition
Data 2
Data 3
t_ph
t_ps
Data 4
Data 5
INT
t_iv
t_ir
A. This figure assumes the command byte has previously been programmed with 00h.
B. Transfer of data can be stopped at any moment by a Stop condition.
C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port. See Figure 22 for these details.
Figure 23. Read From Input Port Register
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