TCA9554_15 Datasheet, PDF (27/38 Pages) Texas Instruments – TCA9554 Low Voltage 8-Bit I2C and SMBus Low-Power I/O Expander With Interrupt Output and Configuration Registers

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11 Layout
TCA9554
SCPS233D – MARCH 2012 – REVISED AUGUST 2015
11.1 Layout Guidelines
For printed circuit board (PCB) layout of the TCA9554, common PCB layout practices should be followed but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I²C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in
the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These
capacitors should be placed as close to the TCA9554 as possible. These best practices are shown in Figure 32.
For the layout example provided in Figure 32, it would be possible to fabricate a PCB with only 2 layers by using
the top layer for signal routing and the bottom layer as a split plane for power (V_CC) and ground (GND). However,
a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to
route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other
internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are
placed directly next to the surface mount component pad which needs to attach to V_CC or GND and the via is
connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace
needs to be routed to the opposite side of the board, but this technique is not demonstrated in Figure 32.
11.2 Layout Example
LEGEND
Power or GND Plane
VIA to Power Plane
VIA to GND Plane
To I2C Master
V_CC
By-pass/De-coupling
capacitors
1
2
3
4
5
6
7
8
GND
A0
A1
A2
P0
P1
P2
P3
GND
VCC
16
SDA
15
SCL
14
INT
13
P7
12
P6
11
P5
10
P4
9
Figure 32. TCA9554 Layout
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