TCA9554_15 Datasheet, PDF (25/38 Pages) Texas Instruments – TCA9554 Low Voltage 8-Bit I2C and SMBus Low-Power I/O Expander With Interrupt Output and Configuration Registers

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10 Power Supply Recommendations
TCA9554
SCPS233D – MARCH 2012 – REVISED AUGUST 2015
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA9554 can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in and Figure 29.
V_CC
Ramp-Down
Ramp-Up
V_CC drops below V_PORF – 50 mV
V_{CC_TRR}
V_{CC_FT}
Time to Re-Ramp
V_{CC_RT}
Time
Figure 29. V_CC is Lowered Below the POR Threshold, Then Ramped Back Up to V_CC
Table 8 specifies the performance of the power-on reset feature for TCA9554 for both types of power-on reset.
Table 8. Recommended Supply Sequencing And Ramp Rates⁽¹⁾
V_{CC_FT}
V_{CC_RT}
V_{CC_TRR}
V_{CC_GH}
V_{CC_GW}
PARAMETER
Fall rate
See Figure 29
Rise rate
See Figure 29
Time to re-ramp (when V_CC drops to V_{POR_MIN} – 50 mV or when
V_CC drops to GND)
See Figure 29
Level that V_CCP can glitch down to, but not cause a functional
disruption when V_{CC_GW} = 1 μs
See Figure 30
Glitch width that will not cause a functional disruption when
V_{CC_GH} = 0.5 × V_CC
See Figure 30
MIN TYP
1
0.1
MAX
UNIT
ms
ms
2
μs
1.2 V
10 μs
(1) All supply sequencing and ramp rate values are measured at T_A = 25°C
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 30 and Table 8 provide more
information on how to measure these specifications.
V_CC
V_{CC_GH}
V_{CC_GW}
Figure 30. Glitch Width and Glitch Height
Time
V_PORR is critical to the power-on reset. V_PORR is the voltage level at which the reset condition is released and all
the registers and the I²C/SMBus state machine are initialized to their default states. The value of power-on-reset
voltage differs based on the V_CC being lowered to or from 0 (V_PORR or V_PORF). Figure 31 and Table 8 provide
more details on this specification.
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