TCA9554_15 Datasheet, PDF (15/38 Pages) Texas Instruments – TCA9554 Low Voltage 8-Bit I2C and SMBus Low-Power I/O Expander With Interrupt Output and Configuration Registers

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Functional Block Diagram (continued)
TCA9554
SCPS233D – MARCH 2012 – REVISED AUGUST 2015
Data From
Shift Register
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Configuration
Register
DQ
FF
C_K Q
Read Pulse
Q1
DQ
FF
C_K Q
Output Port
Register
Input Port
Register
DQ
FF
C_K Q
100 k
Q2
Data From
Shift Register
Write Polarity
Pulse
DQ
FF
C_K Q
Polarity
Inversion
Register
A. At power-on reset, all registers return to default values.
Figure 14. Simplified Schematic Of P0 To P7
Output Port
Register Data
V_CC
P0 to P7
ESD Protection
Diode
GND
Input Port
Register Data
INT
Polarity
Register Data
8.3 Feature Description
8.3.1 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak
pull-up (100 kΩ typ) to V_CC. The input voltage may be raised above V_CC to a maximum of 5.5 V, however it must
be noted that because of the integrated 100 kΩ pull-up resistor it may result in current flow from I/O to VCC pin
(Figure 14).
If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In
this case, there are low impedance paths between the I/O pin and either V_CC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
8.3.2 Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of any P-port I/O configured as an input. After time t_iv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the ports is changed back to the
original state or when data is read from the Input Port register. Resetting occurs in the read mode at the
acknowledge (ACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK clock pulse
can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after
resetting is detected and is transmitted as an interrupt on the INT pin.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register.
The INT output has an open-drain structure and requires pull-up resistor to V_CC.
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