DS92LX1621 Datasheet, PDF (5/44 Pages) National Semiconductor (TI) – 10 - 50 MHz Channel Link III Serializer and Deserializer with Embedded Bi-Directional Control Channel

DS92LX1621 Serializer Pin Descriptions
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
DIN[13:0]
32, 31, 30, 29,
27, 26, 24, 23,
22, 21, 20, 19,
18, 17
Inputs, LVCMOS w/ Parallel data inputs.
pull down
HSYNC
1
Inputs, LVCMOS w/ Parallel data input 14, typically used as Horizontal SYNC Input
pull down
VSYNC
2
Inputs, LVCMOS w/ Parallel data input 15, typically used as Vertical SYNC Input
pull down
PCLK
3
Input, LVCMOS w/ Pixel Clock Input Pin. Strobe edge set by TRFB control register.
pull down
GENERAL PURPOSE INPUT OUTPUT (GPIO)
DIN[3:0]/
GPIO[5:2]
20, 19, 18, 17 Input/Output, Digital DIN[3:0] general-purpose pins can be individually configured as either inputs
or outputs; used to control and respond to various commands.
GPIO[1:0]
16, 15
Input/Output, Digital General-purpose pins can be individually configured as either inputs or
outputs; used to control and respond to various commands.
SERIAL CONTROL BUS - I²C COMPATIBLE
SCL
SDA
M/S
Clock line for the serial control bus communication
4
Input/Output, Digital _{SCL requires an external pull-up resistor to VDDIO.}
5
Input/Output, Open Data line for the serial control bus communication
Drain
SDA requires an external pull-up resistor to V_DDIO.
I²C Mode Select
8
Input, LVCMOS w/
pull down
M/S = L, Master (default); device generates and drives the SCL clock line
M/S = H, Slave; device accepts SCL clock input
CAD
Continuous Address Decoder
Input pin to select the Slave Device Address.
6
Input, analog
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection).
CONTROL AND CONFIGURATION
PDB
Power down Mode Input Pin.
Input, LVCMOS w/ PDB = H, Transmitter is enabled and is ON.
9
pull down
PDB = L, Transmitter is in Sleep (Power Down). When the transmitter is in
the SLEEP state, the PLL is shutdown, and IDD is minimized.
RES
7
Input, LVCMOS w/ Reserved. This pin MUST be tied LOW.
pull down
Channel Link III INTERFACE
DOUT+
13
Input/Output, CML Non-inverting differential output, back-channel input.
DOUT-
12
Input/Output, CML Inverting differential output, back-channel input.
Power and Ground
VDDPLL
10
Power, Analog PLL Power, 1.8V ±5%
VDDT
11
Power, Analog Tx Analog Power, 1.8V ±5%
VDDCML
14
Power, Analog LVDS & BC Dr Power, 1.8V ±5%
VDDD
28
Power, Digital Digital Power, 1.8V ±5%
VDDIO
VSS
25
DAP
Power, Digital
Ground, DAP
Power for input stage, The single-ended inputs are powered from V_DDIO.
DAP must be grounded. Connect to ground plane with at least 9 vias.
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