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DS92LX1621 Datasheet, PDF (11/44 Pages) National Semiconductor (TI) – 10 - 50 MHz Channel Link III Serializer and Deserializer with Embedded Bi-Directional Control Channel
Symbol
Parameter
Conditions
Min
VDDn = 1.89V
CL = 8pF
f = 50 MHz
SSCG[3:0] =
WORST CASE Pattern ON
Deserializer (Rx) Supply
(Figure 5)
Default
IDDR
Current (includes load
Registers
current)
VDDn = 3.6V
f = 50 MHz
CL = 8pF
Default
WORST CASE Pattern Registers
IDDIOR
Deserializer (Rx) VDDIO
VDDIO = 1.89V
Supply Current (includes load CL = 8pF
current)
WORST CASE Pattern
(Figure 5)
f = 50 MHz
Default
Registers
VDDIO = 3.6V
CL = 8pF
Worst Case Pattern
f = 50 MHz
Default
Registers
IDDRZ
IDDIORZ
Deserializer (Rx) Supply
Current Power-down
PDB = 0V; All other
LVCMOS Inputs = 0V
VDDn = 1.89V
VDDIO = 1.89V
VDDIO = 3.6V
Recommended Serializer Timing for PCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
tTCP
tTCIH
Transmit Clock Period
Transmit Clock Input High
Time
10 MHz — 50 MHz
20
0.4T
tTCIL
Transmit Clock Input Low
Time
0.4T
tCLKT
PCLK Input Transition Time
0.5
fosc
Internal oscillator clock
source
Typ
60
53
16
38
42
8
350
Typ
T
0.5T
0.5T
25
Max
96
25
64
400
40
800
Max
100
0.6T
0.6T
3
Units
mA
µA
Units
ns
ns
ns
ns
MHz
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
tLHT
CML Low-to-High
RL = 100Ω (Figure 6)
150
Transition Time
tHLT
CML High-to-Low
RL = 100Ω
Transition Time
(Figure 6)
150
tDIS
Data Input Setup to PCLK
2.0
Serializer Data Inputs (Figure 10)
tDIH
Data Input Hold from PCLK
2.0
tPLD
Serializer PLL Lock Time RL = 100Ω
1
((Note 5, Note 9))
RT = 100Ω
tSD
Serializer Delay
f = 10-50 MHz
Reg Address 0x03h b[0] (TRFB = 1)
6.386T + 5
6.386T +
12
(Figure 12)
tJIND
Serializer Output
Serializer output
Deterministic Jitter
intrinsic deterministic jitter. Measure
with PRBS-7 test pattern. PCLK = 50
0.13
MHz
Max
330
330
2
6.386T +
19.7
Units
ps
ps
ns
ns
ms
ns
UI
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