DS92LX1621 Datasheet, PDF (12/44 Pages) National Semiconductor (TI) – 10 - 50 MHz Channel Link III Serializer and Deserializer with Embedded Bi-Directional Control Channel

Symbol
Parameter
Conditions
Min
Typ
Max
t_JINR
Serializer Output Random Serializer output intrinsic random jitter
Jitter
(cycle-cycle). Alternating – 1,0
0.04
pattern.
Serializer output peak-to-peak jitter
includes deterministic jitter, random
t_JINT
Peak-to-peak Serializer
Output Jitter
jitter, and jitter transfer from serializer
input. Measure with PRBS-7 test
pattern.
0.396
Serializer Jitter Transfer PCLK = 50 MHz
λ_STXBW
Function -3 dB Bandwidth Default Registers
1.9
Serializer Jitter Transfer PCLK = 50 MHz
δ_STX
Function
Default Registers
0.944
Serializer Jitter Transfer PCLK = 50 MHz
δ_STXf
Function Peaking
Default Registers
500
Frequency
Units
UI
UI
MHz
dB
kHz
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ Max
t_RCP
Receiver Output Clock Period t_RCP = t_TCP
PCLK
t_PDC
PCLK Duty Cycle
Default Registers
SSCG[3:0] = OFF
PCLK
20
T
100
45
50
55
t_CLH
LVCMOS Low-to-High Transition V_DDIO: 1.71V to 1.89V or PCLK
Time
3.0V to 3.6V, C_L = 8 pF
t_CHL
LVCMOS High-to-Low Transition (lumped load)
Time
Default Registers
( (Note 10))
1.3
2.0
2.8
1.3
2.0
2.8
t_CLH
LVCMOS Low-to-High Transition V_DDIO: 1.71V to 1.89V or
Time
3.0V to 3.6V, C_L = 8 pF _{Deserializer Data}
1.6
2.4
3.3
(lumped load)
t_CHL
LVCMOS High-to-Low Transition _{Default Registers}
Time
( ) (Note 9)
Outputs
1.6
2.4
3.3
t_ROS
ROUT Setup Data to PCLK
V_DDIO: 1.71V to 1.89V or
0.38T 0.5T
t_ROH
ROUT Hold Data to PCLK
3.0V to 3.6V, CL = 8pF _{Deserializer Data}
(lumped load)
Outputs
Default Registers
0.38T 0.5T
()
t_DD
Deserializer Delay
Default Registers
Register 0x03h b[0]
(RRFB = 1)
10 MHz-50 MHz
4.571T + 4.571T + 4.571T
8
12
+ 16
t_DDLT
t_RJIT
t_RDJ
Deserializer Data Lock Time
Receiver Input Jitter Tolerance
Receiver Clock Jitter
PCLK
SSCG[3:0] = OFF
10 MHz-50 MHz
50 MHz
10 MHz
50 MHz
10
0.53
300
550
120
250
t_DPJ
Deserializer Period Jitter
PCLK
SSCG[3:0] = OFF
10 MHz
50 MHz
425
600
320
480
t_DCCJ
Deserializer Cycle-to-Cycle Clock PCLK
Jitter
SSCG[3:0] = OFF
10 MHz
50 MHz
320
500
300
500
fdev
fmod
Spread Spectrum Clocking
Deviation Frequency
Spread Spectrum Clocking
Modulation Frequency
LVCMOS Output Bus
(Figure 17)
20 MHz-50 MHz
20 MHz-50 MHz
±0.5% to
±2.0%
±9 kHz to
±66 kHz
Units
ns
%
ns
ns
ns
ns
ms
UI
ps
ps
ps
%
kHz
11
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