DS50PCI402_15 Datasheet, PDF (5/38 Pages) Texas Instruments – DS50PCI402 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
Table 1. Pin Descriptions (continued)
Pin Name
RATE
Pin Number
21
Control Pins — Both Modes (LVCMOS)
RXDETA,RXDETB
22,23
PRSNT
52
ENRXDET
26
TXIDLEA,TXIDLEB
Analog
SD_TH
Power
VDD
GND
24,25
27
9, 14,36, 41, 51
DAP
I/O,
Type ^{(1) (2) (3) (4)}
I,FLOAT,
LVCMOS
I, LVCMOS
w/internal
pulldown
I, LVCMOS
I, LVCMOS
w/internal
pulldown
I, FLOAT,
LVCMOS
I, ANALOG
Power
Power
Pin Description
RATE control pin controls the pulse width of de-emphasis of the output.
A Low forces Gen1 (2.5Gbps), High forces Gen 2 (5Gbps),
Open/Floating the rate is internally detected after each exit from idle and
the pulse width is set appropriately. When ENSMBUS= 1 this pin is
disabled and the RATE function is controlled internally by the SMBUS
registers. Refer to Table 5.
The RXDET pins in combination with the ENRXDET pin controls the
receiver detect function. Depending on the input level, a 50Ω or >50KΩ
termination to the power rail is enabled. Refer to Table 7.
Cable Present Detect input. High when a cable is not present per PCIe
Cabling Spec. 1.0. Puts part into low power mode. When low (normal
operation) part is enabled.
Enables pin control of receiver detect function. The default is automatic
RXDET using the internal pulldown. Pin must be pulled high for manual
RXDETA/B operation. Controls individual A and B sides. Refer to
Table 7.
Controls the electrical idle function on corresponding outputs when
enabled. H= electrical Idle, Float=autodetect (Idle on input passed to
output), L=Idle squelch disabled as shown in Table 6.
Threshold select pin for electrical idle detect threshold. Float pin for
default 130mV DIFF p-p, otherwise connect resistor from SD_TH to GND
to set threshold voltage as shown in Table 7.
Power supply pins CML/analog.
Ground pad (DAP - die attach pad).
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