DS50PCI402_15 Datasheet, PDF (10/38 Pages) Texas Instruments – DS50PCI402 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
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CPWRON
CPERST#
CPRSNT# to RESET Removal
DS50PCI402 PRSNT#
Min pulse width HIGH
5 Ps (min)
CPRSNT#
5 ms (min)
0V
0V
RESET Removed and
REFCLK Stable
0V
CREFCLK
Figure 2. Typical PCIe System Timing
The signals shown in the graphic could be easily replicated within the downstream subsystem and used to
externally control the common mode input termination impedance on the DS50PCI402. Often an onboard
microcontroller will be used to handle events like power-up, power-down, power saving modes, and hot insertion.
The microcontroller would use the same information to determine when to enable and disable the DS50PCI402
input termination. In applications that require SMBus control, the microcontroller could also delay any response
to the upstream subsystem to allow sufficient time to correctly program the DS50PCI402 and other devices on
the board.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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