DS50PCI402_15 Datasheet, PDF (3/38 Pages) Texas Instruments – DS50PCI402 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

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Pin Diagram
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
OB_0+ 1
OB_0- 2
OB_1+ 3
OB_1- 4
OB_2+ 5
OB_2- 6
OB_3+ 7
OB_3- 8
VDD 9
IA_0+ ¹⁰
IA_0- ¹¹
IA_1+ 12
IA_1- 13
VDD 14
IA_2+ 15
IA_2- 16
IA_3+ ¹⁷
IA_3- 18
SMBUS AND CONTROL
DAP = GND
45 IB_0+
44 IB_0-
43 IB_1+
42 IB_1-
41 VDD
40 IB_2+
39 IB_2-
38 IB_3+
37 IB_3-
36 VDD
35 OA_0+
34 OA_0-
33 OA_1+
32 OA_1-
31 OA_2+
30 OA_2-
29 OA_3+
28 OA_3-
The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through
multiple (minimum of 8) vias to ensure optimal electrical and thermal performance.
DS50PCI402 Pin Diagram 54 lead
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