DS50PCI402_15 Datasheet, PDF (12/38 Pages) Texas Instruments – DS50PCI402 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
Electrical Characteristics
Over recommended operating supply and temperature ranges with default register settings unless other specified.
(1) (2)
Symbol
POWER ⁽³⁾
Parameter
PD
Power Dissipation
LVCMOS / LVTTL DC SPECIFICATIONS
V_IH
High Level Input
Voltage
V_IL
Low Level Input
Voltage
V_OH
High Level Output
Voltage
V_OL
Low Level Output
Voltage
I_IH
Input High Current
I_IL
Input Low Current
CML RECEIVER INPUTS (IN_n+, IN_n-)
RL_RX-DIFF
Rx package plus Si
differential return loss
RL_RX-CM
Z_RX-DC
Z_RX-DIFF-DC
V_RX-DIFF-DC
Z_{RX-HIGH-IMP-DC -POS}
Common mode Rx
return loss
Rx DC common mode
impedance
Rx DC differential
impedance
Differential Rx peak to
peak voltage
DC Input CM
impedance for V>0
V_{RX-IDLE-DET-DIFF-PP}
Electrical Idle detect
threshold
LPDS OUTPUTS (OUT_n+, OUT_n-)
V_TX-DIFF-PP
Output Voltage Swing
V_OCM
Output Common-Mode
Voltage
Conditions
EQX=Float, DEX=0, VOD=1Vpp
,PRSNT=0
PRSNT=1, ENSMB=0
(4)
(4)
SMBUS open drain V_OH set by
pullup Resistor
I_OL = 4mA
V_IN = 3.6V , LVCMOS
V_IN = 3.6V , w/
FLOAT,PULLDOWN input
V_IN = 0V
V_IN = 0V, w/FLOAT input
0.05GHz – 1.25GHz ⁽⁵⁾
1.25GHz – 2.5GHz ⁽⁵⁾
0.05GHz - 2.5GHz ⁽⁵⁾
Tested at VDD=0
Tested at VDD=0
Tested at DC, TXIDLEx=0
Vin = 0 to 200 mV,
RXDETA/B = 0,
ENSMB = 0, VDD=2.625
SD_TH = float, see Table 5,
(6)
Differential measurement with
OUT_n+ and OUT_n- terminated
by 50Ω to GND AC-Coupled,
Figure 4, ⁽³⁾
Single-ended measurement DC-
Coupled with 50Ω termination, ⁽¹⁾
Min
Typ
Max
800
1000
4
8
2
3.6
0
0.8
0.4
-15
+15
-15
+120
-15
+15
-80
+15
-21
-20
-11.5
40
50
60
85
100
115
0.10
1.2
50
40
175
800
1000
1200
V_DD - 1.4
Units
mW
mW
V
V
V
V
μA
μA
dB
dB
Ω
Ω
V
KΩ
mV_P-P
mV_P-P
V
(1) Typical values represent most likely parametric norms at V_DD = 2.5V, T_A = 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Measured with DEM Select pins configured for 1000mV VOD, see De-emphasis table.
(4) Input edge rate for LVCMOS/FLOAT inputs must be 50ns minimum from 10-90%.
(5) Input Return Loss also uses the setup shown in Figure 6. The blocking / biasing circuit is replaced with a simple AC coupling capacitor
for each input to emulate a typical PCIe application.
(6) Measured at package pins of receiver. Less than 40mV is IDLE, greater than 175mV is ACTIVE. SD_TH pin connected with resistor to
GND overrides this default setting.
12
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