LM3533 Datasheet, PDF (47/53 Pages) Texas Instruments – Complete Lighting Power Solution for Smartphone Handsets

LM3533
voltage spike at the SW pin and the OVP pin due to parasitic inductance in the step current conducting path (V = Ldi/dt). Board
layout guidelines are geared towards minimizing this electric field coupling and conducted noise. Figure 18 highlights these two
noise-generating components.
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FIGURE 18. LM3533's Inductive Boost Converter Showing Pulsed Voltage at SW (High dV/dt) and Current Through
Schottky and COUT (High dI/dt)
The following list details the main (layout sensitive) areas of the LM3533’s inductive boost converter in order of decreasing impor-
tance:
1. Output Capacitor
Schottky Cathode to COUT+
COUT− to GND
2. Schottky Diode
SW Pin to Schottky Anode
Schottky Cathode to COUT+
3. Inductor
SW Node PCB capacitance to other traces
4. Input Capacitor
CIN+ to IN pin
Boost Output Capacitor Selection and Placement
The LM3533's inductive boost converter requires a 1µF output capacitor. The voltage rating of the capacitor depends on the selected
OVP setting. For the 16V setting a 16V capacitor must be used. For the 24V setting a 25V capacitor must be used. For the 32V
setting, a 35V capacitor must be used. For the 40V setting a 50V capacitor must be used. Pay careful attention to the capacitor's
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