LM3533 Datasheet, PDF (32/53 Pages) Texas Instruments – Complete Lighting Power Solution for Smartphone Handsets

LM3533
I²C-Compatible Interface
START AND STOP CONDITIONS
The LM3533 is controlled via an I²C-compatible interface. START and STOP conditions classify the beginning and the end of the
I²C session. A START condition is defined as SDA transitioning from HIGH to LOW while SCL is HIGH. A STOP condition is defined
as SDA transitioning from LOW to HIGH while SCL is HIGH. The I²C master always generates START and STOP conditions. The
I²C bus is considered busy after a START condition and free after a STOP condition. During data transmission the I²C master can
generate repeated START conditions. A START and a repeated START condition are equivalent function-wise. The data on SDA
must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed when SCL
is LOW.
FIGURE 16. Start and Stop Sequences
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I²C-COMPATIBLE ADDRESS
The chip address for the LM3533 is 0110110 (36h) for the -40 device and 0111000 (38h) for the -40A device. After the START
condition, the I²C master sends the 7-bit chip address followed by an eighth read or write bit (R/W). R/W= 0 indicates a WRITE
and R/W = 1 indicates a READ. The second byte following the chip address selects the register address to which the data will be
written. The third byte contains the data for the selected register.
TRANSFERRING DATA
Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte of data must be
followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is generated by the master. The
master releases SDA (HIGH) during the 9th clock pulse. The LM3533 pulls down SDA during the 9th clock pulse signifying an
acknowledge. An acknowledge is generated after each byte has been received.
Table 1 lists the available registers within the LM3533.
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