CC3220MOD_17 Datasheet, PDF (47/88 Pages) Texas Instruments – SimpleLink Wi-Fi CERTIFIED Wireless Module Solutions (S and SF)

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CC3220MOD
SWRS206A – MARCH 2017 – REVISED JUNE 2017
5.13.5.6 ADC
Table 5-13 lists the ADC electrical specifications. See CC32xx ADC Appnote for further information on
using the ADC and for application-specific examples.
Figure 5-15 shows the ADC clock timing diagram.
Internal Ch
Repeats Every 16 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
ADC CLOCK
= 10 MHz
Sampling
4 cycles
SAR Conversion
16 cycles
EXT CHANNEL 0
Sampling
4 cycles
SAR Conversion
16 cycles
INTERNAL CHANNEL
Sampling
4 cycles
SAR Conversion
16 cycles
EXT CHANNEL 1
Figure 5-15. ADC Clock Timing Diagram
Sampling
4 cycles
SAR Conversion
16 cycles
INTERNAL CHANNEL
Table 5-13. ADC Electrical Specifications
PARAMETER
DESCRIPTION
TEST CONDITIONS and
ASSUMPTIONS
MIN
Nbits
Number of bits
Worst-case deviation from
INL
Integral nonlinearity
histogram method over full scale
(not including first and last three
–2.5
LSB levels)
DNL
Differential nonlinearity
Worst-case deviation of any step
from ideal
–1
Input range
0
Driving source
impedance
FCLK
Clock rate
Successive approximation input
clock rate
Input capacitance
ADC Pin 57
Input impedance
ADC Pin 58
ADC Pin 59
ADC Pin 60
Number of channels
F_sample
F_input_max
Sampling rate of each pin
Maximum input signal frequency
SINAD
I_active
Signal-to-noise and distortion
Input frequency DC to 300 Hz
and 1.4 V_pp sine wave input
55
Active supply current
Average for analog-to-digital
during conversion without
reference current
I_PD
Power-down supply current for
core supply
Total for analog-to-digital when
not active (this must be the SoC
level test)
Absolute offset error
FCLK = 10 MHz
Gain error
V_ref
ADC reference voltage
TYP
12
10
12
2.15
0.7
2.12
1.17
4
62.5
60
1.5
1
±2
±2%
1.467
MAX
UNIT
Bits
2.5 LSB
4 LSB
1.4 V
100 Ω
MHz
pF
kΩ
KSPS
31 kHz
dB
mA
µA
mV
V
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