OMAP3515_17 Datasheet, PDF (46/263 Pages) Texas Instruments – Applications Processors

OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾
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BALL
BALL TOP PIN NAME
BOTTOM [1]
[2]
[3]
MODE [4]
AE16
NA
cam_d0
0
AE15
gpio_99
4
safe_mode
7
NA
cam_d1
0
AD17
gpio_100
4
safe_mode
7
NA
gpio_112
4
AE18
safe_mode
7
NA
gpio_114
4
AD16
safe_mode
7
NA
gpio_113
4
AE17
safe_mode
7
NA
gpio_115
4
safe_mode
7
NA
G20
sdrc_a0
0
NA
K20
sdrc_a1
0
NA
J20
sdrc_a2
0
NA
J21
sdrc_a3
0
NA
U21
sdrc_a4
0
NA
R20
sdrc_a5
0
NA
M21
sdrc_a6
0
NA
M20
sdrc_a7
0
NA
N20
sdrc_a8
0
NA
K21
sdrc_a9
0
NA
Y16
sdrc_a10
0
NA
N21
sdrc_a11
0
NA
R21
sdrc_a12
0
NA
AA15
sdrc_a13
0
NA
Y12
sdrc_a14
0
NA
AA18
sdrc_ba0
0
NA
V20
sdrc_ba1
0
NA
Y15
sdrc_cke0
0
safe_mode
7
NA
Y13
sdrc_cke1
0
safe_mode
7
NA
A12
sdrc_clk
0
NA
D1
sdrc_d0
0
NA
G1
sdrc_d1
0
NA
G2
sdrc_d2
0
NA
E1
sdrc_d3
0
NA
D2
sdrc_d4
0
NA
E2
sdrc_d5
0
TYPE [5]
I
I
-
I
I
-
I
-
I
-
I
-
I
-
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IO
IO
IO
IO
IO
IO
IO
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
RESET REL.
MODE [8]
POWER [9]
L
L
7
vdds
HYS [10]
Yes
BUFFER PULLUP
STRENG TH /DOWN IO CELL [13]
(mA) [11] TYPE [12]
4
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
0
0
0
vdds
No
4 ⁽²⁾
NA
LVCMOS
H
1
7
vdds
Yes
4 ⁽²⁾
PU100/
LVCMOS
PD100
H
1
7
vdds
Yes
4 ⁽²⁾
PU100/
LVCMOS
PD100
L
0
0
vdds
Yes
4 ⁽²⁾
PU100/
LVCMOS
PD100
L
Z
0
vdds
Yes
4 ⁽²⁾
PU100/
LVCMOS
PD100
L
Z
0
vdds
Yes
4 ⁽²⁾
PU100/
LVCMOS
PD100
L
Z
0
vdds
Yes
4 ⁽²⁾
PU100/
LVCMOS
PD100
L
Z
0
vdds
Yes
4 ⁽²⁾
PU100/
LVCMOS
PD100
L
Z
0
vdds
Yes
4 ⁽²⁾
PU100/
LVCMOS
PD100
L
Z
0
vdds
Yes
4 ⁽²⁾
PU100/
LVCMOS
PD100
(1) NA in this table stands for Not Applicable.
(2) The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the
selected mode.
46
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