OMAP3515_17 Datasheet, PDF (231/263 Pages) Texas Instruments – Applications Processors

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HDQ
tDW 1
tDW 0
OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
tCYCD
030-097
Figure 6-57. HDQ Write Bit Timing (Command/Address or Data)
HDQ
Break
Command _byte_written
0_(LSB )
1
6
tRSPS
7_(MSB )
Data _byte _received
1
0_(LSB )
6
Figure 6-58. HDQ Communication Timing
030-098
6.6.6.2 1-Wire Protocol
Table 6-112 and Table 6-113 assume testing over the recommended operating conditions (see Figure 6-
59 through Figure 6-61).
PARAMETER
t_PDH
t_PDL
t_RDV + t_REL
Table 6-112. 1-Wire Timing Requirements
DESCRIPTION
Presence pulse delay high
Presence pulse delay low
Read bit-zero time
MIN
68 – t_PDH
MAX
68
102
UNIT
μs
PARAMETER
t_RSTL
t_RSTH
t_SLOT
t_LOW1
t_LOW0
t_REC
t_LOWR
Table 6-113. 1-Wire Switching Characteristics
DESCRIPTION
MIN
TYP
Reset time low
484
Reset time high
484
Write bit cycle time
102
Write bit-one time
1.3
Write bit-zero time
101
Recovery time
134
Read bit strobe time
13
MAX
UNIT
μs
1-WIRE
tRTSL
tPDH
tRSTH
tPDL
Figure 6-59. 1-Wire Break (Reset) Timing
030-099
1-WIRE
tLOWR
tSLOT_and_ tREC
tRDV_and_ tREL
030-100
Figure 6-60. 1-Wire Read Bit Timing (Data)
Copyright © 2008–2013, Texas Instruments Incorporated
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 231
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