OMAP3515_17 Datasheet, PDF (208/263 Pages) Texas Instruments – Applications Processors

OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 6-64. McBSP4 (Set #1) Timing Requirements – Falling Edge and Transmit Mode⁽¹⁾
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B5 t_{su(FSXV-CLKXAE)} Setup time, mcbspx_fsx valid before
3.7
mcbspx_clkx active edge
7.9
ns
B6
t_{h(CLKXAE-FSXV)}
Hold time, mcbspx_fsx valid after mcbspx_clkx
0.5
active edge
0.5
ns
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-66.
Table 6-65. McBSP4 (Set #1) Switching Characteristics – Falling Edge and Transmit Mode⁽¹⁾
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B2
t_{d(CLKXAE-FSXV)}
Delay time, mcbspx_clkx active edge to mcbspx_fsx
0.7
valid
16.6
0.7
33.1
ns
B8
t_{d(CLKXAE-DXV)}
Delay time, mcbspx_clkx active edge to
mcbspx_dx valid
Master
Slave
0.6
16.6
0.6
33.1
ns
0.6
17.3
0.6
33.1
ns
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-66.
Table 6-66. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Falling Edge and Transmit Mode⁽¹⁾
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B5
t_{su(FSXV-CLKXAE)}
Setup time, mcbspx_fsx valid before mcbspx_clkx
5.8
active edge
12.2
ns
B6
t_{h(CLKXAE-FSXV)}
Hold time, mcbspx_fsx valid after mcbspx_clkx
0.5
active edge
0.5
ns
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are
specified in Table 6-66. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).
Table 6-67. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Falling Edge and Transmit
Mode ⁽¹⁾
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN MAX MIN MAX
B2
t_{d(CLKXAE-FSXV)}
Delay time, mcbspx_clkx active edge to mcbspx_fsx valid
0.7
22.2
0.7
44.4
ns
B8
t_{d(CLKXAE-DXV)}
Delay time, mcbspx_clkx active edge to
mcbspx_dx valid
Master
0.6
22.2
0.6
44.4
ns
Slave
0.6
22.2
0.6
44.4
ns
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are
specified in Table 6-66. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).
mcbspx_clkx
mcbspx_fsx
mcbspx_dx
B2
B2
B8
D7
D6
Figure 6-39. McBSP Falling Edge Transmit Timing in Master Mode
D5
030-074
208 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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