OMAP3515_17 Datasheet, PDF (27/263 Pages) Texas Instruments – Applications Processors

OMAP3515, OMAP3503
www.ti.com
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
Note: The pullup/pulldown drive strength is equal to 100 μA except for CBB balls P27, P26, R27, and
R25 and CUS balls N22, N21, N20, and P24, which the pulldown drive strength is equal to 1.8 kΩ.
13. IO CELL: IO cell information.
Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results.
This can be easily prevented with the proper software configuration.
Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾
BALL
BALL TOP PIN NAME MODE [4] TYPE [5]
BOTTOM [1] [2]
[3]
D6
J2
sdrc_d0
0
IO
C6
J1
sdrc_d1
0
IO
B6
G2
sdrc_d2
0
IO
C8
G1
sdrc_d3
0
IO
C9
F2
sdrc_d4
0
IO
A7
F1
sdrc_d5
0
IO
B9
D2
sdrc_d6
0
IO
A9
D1
sdrc_d7
0
IO
C14
B13
sdrc_d8
0
IO
B14
A13
sdrc_d9
0
IO
C15
B14
sdrc_d10 0
IO
B16
A14
sdrc_d11 0
IO
D17
B16
sdrc_d12 0
IO
C17
A16
sdrc_d13 0
IO
B17
B19
sdrc_d14 0
IO
D18
A19
sdrc_d15 0
IO
D11
B3
sdrc_d16 0
IO
B10
A3
sdrc_d17 0
IO
C11
B5
sdrc_d18 0
IO
D12
A5
sdrc_d19 0
IO
C12
B8
sdrc_d20 0
IO
A11
A8
sdrc_d21 0
IO
B13
B9
sdrc_d22 0
IO
D14
A9
sdrc_d23 0
IO
C18
B21
sdrc_d24 0
IO
A19
A21
sdrc_d25 0
IO
B19
D22
sdrc_d26 0
IO
B20
D23
sdrc_d27 0
IO
D20
E22
sdrc_d28 0
IO
A21
E23
sdrc_d29 0
IO
B21
G22
sdrc_d30 0
IO
C21
G23
sdrc_d31 0
IO
H9
AB21
sdrc_ba0 0
O
H10
AC21
sdrc_ba1 0
O
A4
N22
sdrc_a0
0
O
B4
N23
sdrc_a1
0
O
B3
P22
sdrc_a2
0
O
C5
P23
sdrc_a3
0
O
C4
R22
sdrc_a4
0
O
D5
R23
sdrc_a5
0
O
C3
T22
sdrc_a6
0
O
C2
T23
sdrc_a7
0
O
C1
U22
sdrc_a8
0
O
D4
U23
sdrc_a9
0
O
D3
V22
sdrc_a10 0
O
D2
V23
sdrc_a11 0
O
BALL
RESET
STATE [6]
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BALL
RESET REL. POWER [9] HYS [10]
RESET REL. MODE [8]
STATE [7]
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
Z
0
vdds_ mem Yes
0
0
vdds_ mem No
0
0
vdds_ mem No
0
0
vdds_ mem No
0
0
vdds_ mem No
0
0
vdds_ mem No
0
0
vdds_ mem No
0
0
vdds_ mem No
0
0
vdds_ mem No
0
0
vdds_ mem No
0
0
vdds_ mem No
0
0
vdds_ mem No
0
0
vdds_ mem No
0
0
vdds_ mem No
0
0
vdds_ mem No
BUFFER PULLUP
STRENG TH /DOWN
(mA) [11] TYPE [12]
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
PU/ PD
4
NA
4
NA
4
NA
4
NA
4
NA
4
NA
4
NA
4
NA
4
NA
4
NA
4
NA
4
NA
4
NA
4
NA
IO CELL [13]
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
(1) NA in this table stands for "Not Applicable".
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