OMAP3515_17 Datasheet, PDF (167/263 Pages) Texas Instruments – Applications Processors

OMAP3515, OMAP3503
www.ti.com
GPMC_FCLK
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
FA5
FA1
FA9
FA10
FA10
Address 0
FA0
Valid
FA0
Valid
FA16
FA9
FA10
FA10
FA5
FA1
Address 1
FA0
Valid
FA0
Valid
gpmc_nadv_ale
gpmc_noe
gpmc_d[15:0]
FA3
FA12
FA4
FA13
FA3
FA12
FA4
FA13
Data Upper
gpmc_waitx
gpmc_io_dir
FA14
OUT
FA15
IN
FA14
OUT
FA15
IN
030-027
Figure 6-8. GPMC/NOR Flash – Asynchronous Read – 32-bit Timing(1) (2) (3)
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.
FA5 value must be stored inside AccessTime register bit field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Copyright © 2008–2013, Texas Instruments Incorporated
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 167
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