TDA2SX Datasheet, PDF (401/426 Pages) Texas Instruments – ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0

www.ti.com
TDA2SX, TDA2SG
TDA2HG, TDA2HV, TDA2LF
SPRS951A – DECEMBER 2015 – REVISED APRIL 2016
Table 8-48. Bulk Bypass Capacitors
NO.
PARAMETER
1 vdds_ddrx bulk bypass capacitor count⁽¹⁾
MIN
MAX
UNIT
1
Devices
2 vdds_ddrx bulk bypass total capacitance
22
μF
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-
speed (HS) bypass capacitors and DDR3 signal routing.
8.7.3.10 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. Table 8-49 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:
1. Fit as many HS bypass capacitors as possible.
2. Minimize the distance from the bypass cap to the pins/balls being bypassed.
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
5. Minimize via sharing. Note the limites on via sharing shown in Table 8-49.
Table 8-49. High-Speed Bypass Capacitors
NO.
PARAMETER
1 HS bypass capacitor package size⁽¹⁾
2 Distance, HS bypass capacitor to processor being bypassed^(2)(3)(4)
3 processor HS bypass capacitor count per vdds_ddrx rail ⁽¹²⁾
4 processor HS bypass capacitor total capacitance per vdds_ddrx rail ⁽¹²⁾
5 Number of connection vias for each device power/ground ball⁽⁵⁾
6 Trace length from device power/ground ball to connection via⁽²⁾
7 Distance, HS bypass capacitor to DDR device being bypassed⁽⁶⁾
8 DDR3 device HS bypass capacitor count⁽⁷⁾
9 DDR3 device HS bypass capacitor total capacitance⁽⁷⁾
10 Number of connection vias for each HS capacitor⁽⁸⁾⁽⁹⁾
11 Trace length from bypass capacitor connect to connection via⁽²⁾⁽⁹⁾
12 Number of connection vias for each DDR3 device power/ground ball⁽¹⁰⁾
13 Trace length from DDR3 device power/ground ball to connection via⁽²⁾⁽⁸⁾
MIN
TYP
MAX
0201
0402
400
See Table 8-3 and ⁽¹¹⁾
See Table 8-3 and ⁽¹¹⁾
35
70
150
12
0.85
2
35
100
1
35
60
UNIT
10 Mils
Mils
Devices
μF
Vias
Mils
Mils
Devices
μF
Vias
Mils
Vias
Mils
(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer/shorter is better.
(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls,
between the DDR interfaces on the package.
(5) See the Via Channel™ escape for the processor package.
(6) Measured from the DDR3 device power/ground ball to the center of the capacitor package.
(7) Per DDR3 device.
(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
(10) Up to a total of two pairs of DDR power/ground balls may share a via.
(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s
guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.
(12) For more information, see Section 8.3, Core Power Domains
Copyright © 2015–2016, Texas Instruments Incorporated
Applications, Implementation, and Layout 401
Submit Documentation Feedback
Product Folder Links: TDA2SX TDA2SG TDA2HG TDA2HV TDA2LF