TDA2SX Datasheet, PDF (289/426 Pages) Texas Instruments – ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0

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TDA2SX, TDA2SG
TDA2HG, TDA2HV, TDA2LF
SPRS951A – DECEMBER 2015 – REVISED APRIL 2016
Table 7-66 and Figure 7-47 present timing requirements for MIIn in transmit operation.
Table 7-66. Timing Requirements for miin_txclk - MII Operation
NO.
PARAMETER
DESCRIPTION
1
t_{c(TX_CLK)}
Cycle time, miin_txclk
2
t_{w(TX_CLKH)}
Pulse duration, miin_txclk high
3
t_{w(TX_CLKL)}
Pulse duration, miin_txclk low
4
t_{t(TX_CLK)}
Transition time, miin_txclk
SPEED
MIN
10 Mbps
400
100 Mbps
40
10 Mbps
140
100 Mbps
14
10 Mbps
140
100 Mbps
14
10 Mbps
100 Mbps
MAX
260
26
260
26
3
3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
1
2
4
3
miin_txclk
4
Figure 7-47. Clock Timing (GMAC Transmit) - MIIn operation
Table 7-67 and Figure 7-48 present timing requirements for GMAC MIIn Receive 10/100Mbit/s.
Table 7-67. Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
NO.
1
2
PARAMETER
t_{su(RXD-RX_CLK)}
t_{su(RX_DV-RX_CLK)}
t_{su(RX_ER-RX_CLK)}
t_{h(RX_CLK-RXD)}
t_{h(RX_CLK-RX_DV)}
t_{h(RX_CLK-RX_ER)}
DESCRIPTION
Setup time, receive selected signals valid before miin_rxclk
Hold time, receive selected signals valid after miin_rxclk
MIN
MAX
8
8
UNIT
ns
ns
1
2
miin_rxclk (Input)
miin_rxd3−miin_rxd0,
miin_rxdv, miin_rxer (Inputs)
Figure 7-48. GMAC Receive Interface Timing MIIn operation
Table 7-68 and Figure 7-49 present timing requirements for GMAC MIIn Transmit 10/100Mbit/s.
Table 7-68. Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit
10/100 Mbits/s
NO.
PARAMETER
1
t_{d(TX_CLK-TXD)}
t_{d(TX_CLK-TX_EN)}
DESCRIPTION
Delay time, miin_txclk to transmit selected signals valid
MIN
MAX
UNIT
0
25
ns
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Timing Requirements and Switching Characteristics 289
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