TDA2SX Datasheet, PDF (320/426 Pages) Texas Instruments – ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0

TDA2SX, TDA2SG
TDA2HG, TDA2HV, TDA2LF
SPRS951A – DECEMBER 2015 – REVISED APRIL 2016
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mmcj_clk
mmcj_cmd
mmcj_dat[3:0]
HS1
HS2H
HS2L
HS5
HS6
HS5
HS6
Figure 7-79. MMC/SD/SDIOj in - High Speed - Transmitter Mode
MMC3/4_10
7.22.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
Figure 7-80, Figure 7-81, and Table 7-121, through Table 7-124 present Timing requirements and
Switching characteristics for MMC3 and MMC4 - SD and SDIO SDR12 in receiver and transmitter mode.
Table 7-121. Timing Requirements for MMC3 - SDR12 Mode ⁽¹⁾
NO. PARAMETER
SDR125 t_{su(cmdV-clkH)}
SDR126 t_h(clkH-cmdV)
SDR127 t_su(dV-clkH)
SDR128 t_h(clkH-dV)
(1) i in [i:0] = 7
DESCRIPTION
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
MIN
27.33
1.6
27.33
1.6
MAX
UNIT
ns
ns
ns
ns
Table 7-122. Switching Characteristics for MMC3 - SDR12 Mode ⁽²⁾
NO. PARAMETER
SDR120 fop(clk)
SDR121 t_w(clkH)
DESCRIPTION
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
SDR122 t_w(clkL)
Pulse duration, mmc3_clk low
SDR123 t_d(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
SDR124 t_d(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
MIN
0.5*P-
0.270 ⁽¹⁾
0.5*P-
0.270 ⁽¹⁾
-19.13
-19.13
MAX
24
UNIT
MHz
ns
ns
16.93 ns
16.93 ns
Table 7-123. Timing Requirements for MMC4 - SDR12 Mode ⁽¹⁾
NO. PARAMETER
SDR125 t_{su(cmdV-clkH)}
SDR126 t_h(clkH-cmdV)
SDR127 t_su(dV-clkH)
SDR128 t_h(clkH-dV)
(1) j in [i:0] = 3
DESCRIPTION
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
MIN
27.33
1.6
27.33
1.6
MAX
UNIT
ns
ns
ns
ns
Table 7-124. Switching Characteristics for MMC4 - SDR12 Mode ⁽²⁾
NO. PARAMETER
SDR120 fop(clk)
SDR121
SDR122
SDR125
SDR126
t_w(clkH)
t_w(clkL)
t_d(clkL-cmdV)
t_d(clkL-dV)
DESCRIPTION
Operating frequency, mmc4_clk
Pulse duration, mmc4_clk high
Pulse duration, mmc4_clk low
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
MIN
0.45*P ⁽¹⁾
0.45*P ⁽¹⁾
-19.13
-19.13
MAX
24
16.93
16.93
UNIT
MHz
ns
ns
ns
ns
320 Timing Requirements and Switching Characteristics
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