TDA2SX Datasheet, PDF (255/426 Pages) Texas Instruments – ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0

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spim_cs(OUT)
PHA=0
EPOL=1
spim_sclk(OUT) ^POL=0
POL=1
spim_sclk(OUT)
spim_d(IN)
TDA2SX, TDA2SG
TDA2HG, TDA2HV, TDA2LF
SPRS951A – DECEMBER 2015 – REVISED APRIL 2016
SM8
SM1
SM2
SM3
SM3
SM1
SM2
SM4
Bit n-1
SM5
SM4
Bit n-2
SM5
Bit n-3
Bit n-4
Bit 0
SM9
spim_cs(OUT)
PHA=1
EPOL=1
spim_sclk(OUT) ^POL=0
SM8
POL=1
spim_sclk(OUT)
SM2
SM1
SM3
SM1
SM3
SM2
SM9
spim_d(IN)
SM5
SM4
Bit n-1
SM4
SM5
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 7-27. McSPI - Master Mode Receive
Table 7-38, Figure 7-28 and Figure 7-29 present Timing Requirements for McSPI - Slave Mode.
NO.
SS1
SS2
SS3
SS4
SS5
SS6
PARAMETER
t_c(SPICLK)
t_w(SPICLKL)
t_w(SPICLKH)
t_{su(SIMO-SPICLK)}
t_{h(SPICLK-SIMO)}
t_{d(SPICLK-SOMI)}
SS7
SS8
SS9
t_d(CS-SOMI)
t_{su(CS-SPICLK)}
t_h(SPICLK-CS)
Table 7-38. Timing Requirements for SPI - Slave Mode
DESCRIPTION
Cycle time, spi_sclk ^{(1) (2)}
Typical Pulse duration, spi_sclk low ⁽¹⁾
Typical Pulse duration, spi_sclk high ⁽¹⁾
Setup time, spi_d[x] valid before spi_sclk active edge ⁽¹⁾
Hold time, spi_d[x] valid after spi_sclk active edge ⁽¹⁾
Delay time, spi_sclk active edge to mcspi_somi transition ⁽¹⁾
Delay time, spi_cs[x] active edge to mcspi_somi transition ⁽¹⁾
Setup time, spi_cs[x] valid before spi_sclk first edge ⁽¹⁾
Hold time, spi_cs[x] valid after spi_sclk last edge ⁽¹⁾
MODE
(3)
MIN
62.5
0.45*P ⁽⁴⁾
0.45*P ⁽⁴⁾
5
5
SPI1/2/3
2
SPI4
2
5
5
MAX
26.1
18
20.95
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Timing Requirements and Switching Characteristics 255
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