TDA2SX Datasheet, PDF (371/426 Pages) Texas Instruments – ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0

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TDA2SX, TDA2SG
TDA2HG, TDA2HV, TDA2LF
SPRS951A – DECEMBER 2015 – REVISED APRIL 2016
Table 8-14. USB1 Routing Recommendations (continued)
Item
Vias
Description
Max 2 vias per signal trace. If vias are required, place vias close to
the AC Caps and CMFs. Vias under the SoC grid array may be used
if necessary to route signals away from BGA pattern.
Reason
Vias significantly degrade signal
integrity at 2.5GHz
Figure 8-41 presents an example layout, demonstrating the “carve GND” concept.
AC Cap
AC Cap
CMF
CMF
Top Layer: Routing from SoC through
AC Caps, CMF, and ESD to connector.
Layer2, GND: Gaps carved in GND underneath
AC Caps, CMF, ESD, and connector.
Layer3, Signal: Implement as keep-out
zone underneath carved GND areas.
Layer4, GND Plane underneath AC Caps,
CMF, ESD, and connector.
Figure 8-41. USB 3.0 Example “carve GND” layout
SPRS85x_PCB_USB30_3
8.5.4 HDMI Board Design and Layout Guidelines
This section provides the timing specification for the HDMI interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. TI has performed the simulation and system design work to ensure the HDMI interface
requirements are met. The design rules stated within this document are targeted at resolutions less than
or equal to 1080p60 with 8-bit color; deep color (10-bit) requires further signal integrity optimization.
8.5.4.1 HDMI Interface Schematic
The HDMI bus is separated into three main sections (HDMI Ethernet and the optional Audio Return
Channel are not specifically supported by this Device):
1. Transition Minimized Differential Signaling (TMDS) high speed digital video interface
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Applications, Implementation, and Layout 371
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