TDA2SX Datasheet, PDF (188/426 Pages) Texas Instruments – ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0

TDA2SX, TDA2SG
TDA2HG, TDA2HV, TDA2LF
SPRS951A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
NOTE
The following DPLLs are controlled by the clock manager located in the always-on Core
power domain (CM_CORE_AON):
• DPLL_MPU, DPLL_IVA, DPLL_CORE, DPLL_ABE, DPLL_DDR, DPLL_GMAC,
DPLL_PCIE_REF, DPLL_PER, DPLL_USB, DPLL_EVE, DPLL_DSP, DPLL_GPU,
APLL_PCIE_REF.
For more information on CM_CORE_AON and CM_CORE or PRCM DPLLs, see Power, Reset, and Clock
Management (PRCM) chapter of the Device TRM.
The following DPLLs are not managed by the PRCM:
• DPLL_VIDEO1; (It is controlled from DSS)
• DPLL_VIDEO2; (It is controlled from DSS)
• DPLL_HDMI; (It is controlled from DSS)
• DPLL_SATA; (It is controlled from SATA)
• DPLL_DEBUG; (It is controlled from DEBUGSS)
• DPLL_USB_OTG_SS; (It is controlled from OCP2SCP1)
NOTE
For more information for not controlled from PRCM DPLL’s see the related chapters in TRM.
6.2.1 DPLL Characteristics
The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated
the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass
mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when
selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next
paragraph.
The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and
CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are
generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock,
CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with
the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through
an asynchronous multplexing.
For more information, see the Power Reset Controller Management chapter of the Device TRM.
Table 6-12 summarizes DPLL type described in Section 6.2, DPLLs, DLLs Specifications introduction.
DPLL NAME
DPLL_ABE
DPLL_CORE
DPLL_DEBUGSS
DPLL_DSP
DPLL_EVE
DPLL_GMAC
DPLL_HDMI
DPLL_IVA
DPLL_MPU
DPLL_PER
Table 6-12. DPLL Control Type
TYPE
Table 6-13 (Type A)
Table 6-13 (Type A)
Table 6-13 (Type A)
Table 6-13 (Type A)
Table 6-13 (Type A)
Table 6-13 (Type A)
Table 6-14 (Type B)
Table 6-13 (Type A)
Table 6-13 (Type A)
Table 6-13 (Type A)
CONTROLLED BY PRCM
Yes⁽¹⁾
Yes⁽¹⁾
No⁽²⁾
Yes⁽¹⁾
Yes⁽¹⁾
Yes⁽¹⁾
No⁽²⁾
Yes⁽¹⁾
Yes⁽¹⁾
Yes⁽¹⁾
188 Clock Specifications
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