TMS320C6743_14 Datasheet, PDF (4/151 Pages) Texas Instruments – Fixed- and Floating-Point Digital Signal Processor

TMS320C6743
SPRS565D – APRIL 2009 – REVISED JUNE 2014
1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the TMS320C6743 device.
Input
Clock(s)
System Control
PLL/Clock
Generator
w/OSC
General-
Purpose
Timer
General-
Purpose
Timer
(Watchdog)
JTAG Interface
Memory
Protection
Power/Sleep
Controller
Pin
Multiplexing
DSP Subsystem
C674x
DSP CPU
AET
32KB 32KB
L1 Pgm L1 RAM
BOOT ROM
Switched Central Resource (SCR)
Peripherals
DMA
GPIO
EDMA3
Control Timers
Audio Ports
Serial Interfaces
McASP
w/FIFO
(2)
I²C
(2)
SPI
UART
(1)
(2)
PRU
Subsystem
Connectivity
External Memory Interfaces
ePWM
(3)
eCAP
(3)
eQEP
(2)
(10/100)
EMAC MDIO
(RMII)
MMC/SD
(8b)
EMIFA(8b)
NAND/Flash
EMIFB
SDRAM Only
(16b)
(1) Not all peripherals are available at the same time due to multiplexing.
Figure 1-1. TMS320C6743 Functional Block Diagram
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TMS320C6743 Fixed- and Floating-Point Digital Signal Processor
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