TMS320C6743_14 Datasheet, PDF (124/151 Pages) Texas Instruments – Fixed- and Floating-Point Digital Signal Processor

TMS320C6743
SPRS565D – APRIL 2009 – REVISED JUNE 2014
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6.22.2 I2C Peripheral Registers Description(s)
Table 6-69 is the list of the I2C registers.
I2C0
BYTE ADDRESS
0x01C2 2000
0x01C2 2004
0x01C2 2008
0x01C2 200C
0x01C2 2010
0x01C2 2014
0x01C2 2018
0x01C2 201C
0x01C2 2020
0x01C2 2024
0x01C2 2028
0x01C2 202C
0x01C2 2030
0x01C2 2034
0x01C2 2038
0x01C2 2048
0x01C2 204C
0x01C2 2050
0x01C2 2054
0x01C2 2058
0x01C2 205C
Table 6-69. Inter-Integrated Circuit (I2C) Registers
I2C1
BYTE ADDRESS
0x01E2 8000
0x01E2 8004
0x01E2 8008
0x01E2 800C
0x01E2 8010
0x01E2 8014
0x01E2 8018
0x01E2 801C
0x01E2 8020
0x01E2 8024
0x01E2 8028
0x01E2 802C
0x01E2 8030
0x01E2 8034
0x01E2 8038
0x01E2 8048
0x01E2 804C
0x01E2 8050
0x01E2 8054
0x01E2 8058
0x01E2 805C
REGISTER NAME
ICOAR
ICIMR
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
ICEMDR
ICPSC
REVID1
REVID2
ICPFUNC
ICPDIR
ICPDIN
ICPDOUT
ICPDSET
ICPDCLR
REGISTER DESCRIPTION
I2C Own Address Register
I2C Interrupt Mask Register
I2C Interrupt Status Register
I2C Clock Low-Time Divider Register
I2C Clock High-Time Divider Register
I2C Data Count Register
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
I2C Revision Identification Register 1
I2C Revision Identification Register 2
I2C Pin Function Register
I2C Pin Direction Register
I2C Pin Data In Register
I2C Pin Data Out Register
I2C Pin Data Set Register
I2C Pin Data Clear Register
6.22.3 I2C Electrical Data/Timing
6.22.3.1 Inter-Integrated Circuit (I2C) Timing
Table 6-70 and Table 6-71 assume testing over recommended operating conditions (see Figure 6-45 and
Figure 6-46).
NO.
1 t_c(SCL)
2 t_{su(SCLH-SDAL)}
3 t_h(SCLL-SDAL)
4 t_w(SCLL)
5 t_w(SCLH)
6 t_su(SDA-SCLH)
7 t_h(SDA-SCLL)
Table 6-70. I2C Input Timing Requirements
Cycle time, I2Cx_SCL
Setup time, I2Cx_SCL high before I2Cx_SDA low
Hold time, I2Cx_SCL low after I2Cx_SDA low
Pulse duration, I2Cx_SCL low
Pulse duration, I2Cx_SCL high
Setup time, I2Cx_SDA before I2Cx_SCL high
Hold time, I2Cx_SDA after I2Cx_SCL low
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
MIN
MAX UNIT
10
μs
2.5
4.7
μs
0.6
4
μs
0.6
4.7
μs
1.3
4
μs
0.6
250
ns
100
0
μs
0
0.9
124 Peripheral Information and Electrical Specifications
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