TMS320C6743_14 Datasheet, PDF (1/151 Pages) Texas Instruments – Fixed- and Floating-Point Digital Signal Processor

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TMS320C6743
SPRS565D – APRIL 2009 – REVISED JUNE 2014
TMS320C6743 Fixed- and Floating-Point Digital Signal Processor
1 TMS320C6743 Fixed- and Floating-Point Digital Signal Processor
1.1 Features
1
• Applications
– Networking
– High-Speed Encoding
– Professional Audio™
• Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library
• 375-MHz TMS320C674x Fixed- and Floating-Point
VLIW DSP Core
– Load-Store Architecture with Nonaligned
Support
– 64 General-Purpose Registers (32-Bit)
– Six ALU (32- and 40-Bit) Functional Units
• Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
• Supports up to Four SP Additions Per Clock,
Four DP Additions Every 2 Clocks
• Supports up to Two Floating Point (SP or
DP) Reciprocal Approximation (RCPxP) and
Square-Root Reciprocal Approximation
(RSQRxP) Operations Per Cycle
– Two Multiply Functional Units
• Mixed-Precision IEEE Floating Point Multiply
Supported up to:
– 2 SP x SP -> SP Per Clock
– 2 SP x SP -> DP Every Two Clocks
– 2 SP x DP -> DP Every Three Clocks
– 2 DP x DP -> DP Every Four Clocks
• Fixed-Point Multiply Supports Two 32 x 32-
Bit Multiplies, Four 16 x 16-Bit Multiplies, or
Eight 8 x 8-Bit Multiplies per Clock Cycle,
and Complex Multiples
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop
Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and
Program Redirection
• C674x Instruction Set Features
– Superset of the C67x+ and C64x+ ISAs
– 3000 MIPS and 2250 MFLOPS C674x
– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
1
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
• C674x Two-Level Cache Memory Architecture
– 32KB of L1P Program RAM/Cache
– 32KB of L1D Data RAM/Cache
– 128KB of L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct Memory Access Controller 3
(EDMA3):
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
• 3.3-V LVCMOS I/Os
• Two External Memory Interfaces:
– EMIFA
• NOR (8-Bit-Wide Data)
• NAND (8-Bit-Wide Data)
– EMIFB
• 16-bit SDRAM, up to 128MB
• Two Configurable 16550-Type UART Modules:
– UART0 with Modem Control Signals
– 16-Byte FIFO
– 16x or 13x Oversampling Option
• One Serial Peripheral Interface (SPI) with One
Chip Select
• Multimedia Card (MMC)/Secure Digital (SD)
• Two Master and Slave Inter-Integrated Circuit (I²C
Bus™)
• Programmable Real-Time Unit Subsystem
(PRUSS)
– Two Independent Programmable Real-Time Unit
(PRU) Cores
• 32-Bit Load-Store RISC Architecture
• 4KB of Instruction RAM per Core
• 512 Bytes of Data RAM per Core
• PRUSS can be Disabled Through Software
to Save Power
• Register 30 of each PRU is Exported from
the Subsystem in Addition to the Normal R31
Output of the PRU Cores
– Standard Power-Management Mechanism
• Clock Gating
• Entire Subsystem Under a Single PSC Clock
Gating Domain
– Dedicated Interrupt Controller
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.