TMS320C6743_14 Datasheet, PDF (125/151 Pages) Texas Instruments – Fixed- and Floating-Point Digital Signal Processor

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TMS320C6743
SPRS565D – APRIL 2009 – REVISED JUNE 2014
NO.
8 t_w(SDAH)
9 t_r(SDA)
10 t_r(SCL)
11 t_f(SDA)
12 t_f(SCL)
13 t_{su(SCLH-SDAH)}
14 t_w(SP)
15 C_b
Table 6-70. I2C Input Timing Requirements (continued)
Pulse duration, I2Cx_SDA high
Rise time, I2Cx_SDA
Rise time, I2Cx_SCL
Fall time, I2Cx_SDA
Fall time, I2Cx_SCL
Setup time, I2Cx_SCL high before I2Cx_SDA high
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
MIN
4.7
1.3
20 + 0.1C_b
20 + 0.1C_b
20 + 0.1C_b
20 + 0.1C_b
4
0.6
N/A
0
Table 6-71. I2C Switching Characteristics⁽¹⁾
NO.
PARAMETER
MIN
16 t_c(SCL)
Cycle time, I2Cx_SCL
Standard Mode
10
Fast Mode
2.5
Standard Mode
4.7
17 t_{su(SCLH-SDAL)}
Setup time, I2Cx_SCL high before I2Cx_SDA low
Fast Mode
0.6
Standard Mode
4
18 t_h(SDAL-SCLL)
Hold time, I2Cx_SCL low after I2Cx_SDA low
Fast Mode
0.6
19 t_w(SCLL)
Pulse duration, I2Cx_SCL low
Standard Mode
4.7
Fast Mode
1.3
20 t_w(SCLH)
Pulse duration, I2Cx_SCL high
Standard Mode
4
Fast Mode
0.6
Standard Mode
250
21 t_{su(SDAV-SCLH)}
Setup time, I2Cx_SDA valid before I2Cx_SCL high
Fast Mode
100
Standard Mode
0
22 t_h(SCLL-SDAV)
Hold time, I2Cx_SDA valid after I2Cx_SCL low
Fast Mode
0
23 t_w(SDAH)
Pulse duration, I2Cx_SDA high
Standard Mode
4.7
Fast Mode
1.3
Standard Mode
4
28 t_{su(SCLH-SDAH)}
Setup time, I2Cx_SCL high before I2Cx_SDA high
Fast Mode
0.6
(1) I2C must be configured correctly to meet the timings in Table 6-71.
MAX UNIT
μs
1000
ns
300
1000
ns
300
300
ns
300
300
ns
300
μs
ns
50
400
pF
400
MAX UNIT
μs
μs
μs
μs
μs
ns
μs
0.9
μs
μs
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Peripheral Information and Electrical Specifications 125
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