TMS320C6743_14 Datasheet, PDF (140/151 Pages) Texas Instruments – Fixed- and Floating-Point Digital Signal Processor

TMS320C6743
SPRS565D – APRIL 2009 – REVISED JUNE 2014
www.ti.com
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz (for example, "Blank" is the default).
Figure 7-1 provides a legend for reading the complete device name for any TMS320C674x member.
TMS 320 C6743 ( ) ZKB ( ) ( )
PREFIX
TMX = Experimental Device
TMS = Qualified Device
DEVICE FAMILY
320 = TMS320™ DSP Family
DEVICE
C6743
SILICON REVISION
Blank = Revision 1.0
A = Revision 1.1
B = Revision 2.0
C = Revision 2.1
D = Revision 3.0
A. BGA = Ball Grid Array.
DEVICE SPEED RANGE
2 = 200 MHz
3 = 300 MHz for revision 1.x
3 = 375 MHz for revision 2.x, 3.0
TEMPERATURE RANGE (JUNCTION)
Blank = 0°C to 90°C, Commercial Grade
T = –40°C to 125°C, Automotive Grade
PACKAGE TYPE^(A)
ZKB = 256-Pin Plastic BGA, with Pb-free Soldered
Balls [Green]
PTP = 176-Pin Thin Quad Flat Pack (TQFP)
[PTP Suffix], 0.5 mm Pin Pitch
Figure 7-1. Device Nomenclature
7.2 Documentation Support
The following documents describe the TMS320C6743 Low-power digital signal processor. Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com.
DSP Reference Guides
SPRUG82
TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the
TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications.
Shows how to maintain coherence with external memory, how to use DMA to reduce
memory latencies, and how to optimize your code to improve cache efficiency. The internal
memory architecture in the C674x DSP is organized in a two-level hierarchy consisting of a
dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level.
Accesses by the CPU to the these first level caches can complete without CPU pipeline
stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next
lower memory level, L2 or external memory.
SPRUFE8
TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal
processors (DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with
added functionality and an expanded instruction set.
140 Device and Documentation Support
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