LP2996A Datasheet, PDF (4/29 Pages) Texas Instruments – DDR Termination Regulator

LP2996A
SNOSCY7 – JUNE 2014
www.ti.com
Pin Descriptions (continued)
V_REF
V_TT
V_REF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to provide the
reference voltage for the Northbridge chipset and memory. Since these inputs are typically an extremely high
impedance, there should be little current drawn from V_REF. For improved performance, an output bypass capacitor can
be used, located close to the pin, to help with noise. A ceramic capacitor in the range of 0.1 µF to 0.01 µF is
recommended. This output remains active during the shutdown state and thermal shutdown events for the suspend to
RAM functionality.
V_TT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while
regulating the output precisely to VDDQ / 2. The LP2996A is designed to handle peak transient currents of up to ± 3 A
with a fast transient response. The maximum continuous current is a function of V_IN and can be viewed in the Typical
Performance Characteristics section. If a transient is expected to last above the maximum continuous current rating for
a significant amount of time then the output capacitor should be sized large enough to prevent an excessive voltage
drop. Despite the fact that the LP2996A is designed to handle large transient output currents it is not capable of
handling these for long durations, under all conditions. The reason for this is the standard packages are not able to
thermally dissipate the heat as a result of the internal power loss. If large currents are required for longer durations,
then care should be taken to ensure that the maximum junction temperature is not exceeded. Proper thermal derating
should always be used (please refer to the Thermal Dissipation section). If the junction temperature exceeds the
thermal shutdown point than V_TT will tri-state until the part returns below the hysteretic trip-point.
6 Specifications
6.1 Absolute Maximum Ratings ⁽¹⁾⁽²⁾
over operating free-air temperature range (unless otherwise noted)
AVIN to GND
PVIN to GND
VDDQ ⁽³⁾
Junction Temperature
Lead Temperature (Soldering, 10 sec)
MIN
MAX
UNIT
−0.3
6
V
–0.3
AVIN
−0.3
6
V
150
°C
260
°C
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which
the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions
see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
MIN
T_stg
Storage temperature range
−65
V_(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins ⁽¹⁾
MAX
150
1
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
UNIT
°C
kV
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Junction Temp. Range⁽¹⁾
0
AVIN to GND
2.2
PVIN Supply Voltage
0
SD Input Voltage
0
(1) At elevated temperatures, devices must be derated based on thermal resistance.
NOM
MAX
125
5.5
AVIN
AVIN
UNIT
°C
V
4
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