LP2996A Datasheet, PDF (17/29 Pages) Texas Instruments – DDR Termination Regulator

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LP2996A
SNOSCY7 – JUNE 2014
Typical Application (continued)
8.2.6 HSTL Applications
The LP2996A can be easily adapted for HSTL applications by connecting V_DDQ to the 1.5 V rail. This will produce
a V_TT and V_REF voltage of approximately 0.75 V for the termination resistors. AVIN and PVIN should be
connected to a 2.5 V rail for optimal performance.
SD
VDDQ = 1.5V
VDD = 2.5V
+
CIN
LP2996
SD
VDDQ
VREF
AVIN
VSENSE
PVIN
VTT
GND
+
CREF
VREF = 0.75V
+
COUT
VTT = 0.75V
Figure 28. HSTL Application
8.2.7 QDR Applications
Quad data rate (QDR) applications utilize multiple channels for improved memory performance. However, this
increase in bus lines has the effect of increasing the current levels required for termination. The recommended
approach in terminating multiple channels is to use a dedicated LP2996A for each channel. This simplifies layout
and reduces the internal power dissipation for each regulator. Separate V_REF signals can be used for each DIMM
bank from the corresponding regulator with the chipset reference provided by a local resistor divider or one of the
LP2996A signals. Because V_REF and V_TT are expected to track and the part to part variations are minor, there
should be little difference between the reference signals of each LP2996A.
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