LP2996A Datasheet, PDF (19/29 Pages) Texas Instruments – DDR Termination Regulator

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10 Layout
LP2996A
SNOSCY7 – JUNE 2014
10.1 Layout Guidelines
1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin.
2. V_SENSE should be connected to the V_TT termination bus at the point where regulation is required. For
motherboard applications an ideal location would be at the center of the termination bus.
3. V_DDQ can be connected remotely to the V_DDQ rail input at either the DIMM or the Chipset. This provides the
most accurate point for creating the reference voltage.
4. For improved thermal performance excessive top side copper should be used to dissipate heat from the
package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these
can be located underneath the package if manufacturing standards permit.
5. Care should be taken when routing the V_SENSE trace to avoid noise pickup from switching I/O signals. A
0.1uF ceramic capacitor located close to the _SENSE can also be used to filter any unwanted high frequency
signal. This can be an issue especially if long _SENSE traces are used.
6. V_REF should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This
capacitor should be located as close as possible to the V_REF pin.
10.2 Layout Examples
The LP2996A layout is very similar to the LP2998/Q layout. This is because the main difference between the two
IC's is the wider temperature range, -40°C to 125°C, which the LP2998/Q offers. As such, the below example
shows the layout from a LP2998EVM. These layout examples can be used to evaluate the LP2996A.
Figure 29. LP2998EVM SO PowerPAD Layout Example (Front)
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