LP2996A Datasheet, PDF (10/29 Pages) Texas Instruments – DDR Termination Regulator

LP2996A
SNOSCY7 – JUNE 2014
7 Detailed Description
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7.1 Overview
The LP2996A linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-
SDRAM. The device also supports DDR2, DDR3 and DDR3L VTT bus termination with V_DDQ min of 1.35V. The
device contains a high-speed operational amplifier to provide excellent response to load transients. The output
stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the
application as required for DDR-SDRAM termination.
7.2 Functional Block Diagram
SD
V_DDQ
AV_IN
PV_IN
50k
V_REF
+
-
-
50k
+
V_TT
V_SENSE
GND
7.3 Feature Description
The LP2996A is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2. The
output, V_TT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The
output stage has been designed to maintain excellent load regulation while preventing shoot through. The
LP2996A also incorporates two distinct power rails that separates the analog circuitry from the power output
stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits the
LP2996A to provide a termination solution for DDR2-SDRAM, DDR3-SDRAM and DDR3L-SDRAM memory. For
wide temperature designs, the LP2998/8Q is recommended for all DDR applications.
7.4 Device Functional Modes
The LP2996A can also be used to provide a termination voltage for other logic schemes such as SSTL-3 or
HSTL. Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission
across the memory bus. This termination scheme is essential to prevent data error from signal reflections while
transmitting at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class
II single parallel termination. This involves one R_S series resistor from the chipset to the memory and one R_T
termination resistor. Typical values for R_S and R_T are 25 Ω, although these can be changed to scale the current
requirements from the LP2996A. This implementation can be seen below in Figure 16.
VDD
VTT
CHIPSET
RT
MEMORY
RS
VREF
Figure 16. SSTL-Termination Scheme
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