BQ25601 Datasheet, PDF (4/60 Pages) Texas Instruments – I2C Controlled 3-A, Single-Cell Battery Charger for High Input Voltage and Narrow Voltage DC (NVDC) Power Path Management

bq25601
SLUSCK5 – MARCH 2017
6 Pin Configuration and Functions
RTW Package
24-Pin WQFN
Top View
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VAC
PSEL
PG
STAT
SCL
SDA
1
18
2
17
3
Thermal
16
4
Pad
15
5
14
6
13
7 8 9 10 11 12
GND
GND
SYS
SYS
BAT
BAT
(Not to scale)
NAME
BAT
BTST
CE
GND
INT
NC
PG
PMID
PSEL
QON
REGN
SCL
SDA
Pin
NO.
13
14
21
9
17
18
7
8
10
3
23
2
12
22
5
6
TYPE ⁽¹⁾
Pin Functions
DESCRIPTION
P
Battery connection point to the positive terminal of the battery pack. The internal BATFET and current sensing is
connected between SYS and BAT. Connect a 10 µF close to the BAT pin.
P
PWM high side driver positive supply. Internally, the BTST pin is connected to the cathode of the boost-strap
diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
DI
Charge enable pin. When this pin is driven low, battery charging is enabled.
—
Ground pins.
DO
Open-drain interrupt Output. Connect the INT to a logic rail through 10-kΩ resistor. The INT pin sends an active
low, 256-µs pulse to host to report charger device status and fault.
—
No Connect. Keep the pins float.
Open drain active low power good indicator. Connect to the pull up rail through 10-kΩ resistor. LOW indicates a
DO good input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current
limit is above 30 mA.
DO
Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Put 10 μF ceramic
capacitor on PMID to GND.
Power source selection input. Set 500 mA input current limit by pulling this pin high and set 2.4A input current limit
DI
by pulling this pin low. Once the device gets into host mode, the host can program different input current limits to
IINDPM register.
BATFET enable/reset control input. When BATFET is in ship mode, a logic low of t_SHIPMODE duration turns on
DI
BATFET to exit shipping mode. When VBUS is not plugged-in, a logic low of t_{QON_RST} (minimum 8 s) duration
resets SYS (system power) by turning BATFET off for t_{BATFET_RST} (minimum 250 ms) and then re-enable BATFET
to provide full system power reset. The pin contains an internal pull-up to maintain default high logic.
LSFET driver and internal supply output. Internally, REGN is connected to the anode of the boost-strap diode.
P
Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to GND. The capacitor should be placed close to the
IC.
DI
I²C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
DIO I²C interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P
= Power
4
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