BQ25601 Datasheet, PDF (18/60 Pages) Texas Instruments – I2C Controlled 3-A, Single-Cell Battery Charger for High Input Voltage and Narrow Voltage DC (NVDC) Power Path Management

bq25601
SLUSCK5 – MARCH 2017
www.ti.com
Device Functional Modes (continued)
After input source type detection is completed, an INT pulse is asserted to the host. in addition, the following
registers and pin are changed:
1. input Current Limit (IINDPM) register is changed to set current limit
2. PG_STAT bit is set
3. VBUS_STAT bit is updated to indicate USB or other input source
The host can over-write IINDPM register to change the input current limit if needed. The charger input current is
always limited by the IINDPM register.
8.4.3.3.1 PSEL pins sets input current limit in bq25601
The bq25601 has PSEL pin for input current limit setting to interface with USB PHY. It directly takes the USB
PHY device output to decide whether the input is USB host or charging port. When the device operates in host-
control mode, the host needs to IINDET_EN bit to read the PSEL value and update the IINDPM register. When
the device is in default mode, PSEL value updates IINDPM in real time.
input Detection
USB SDP
Adapter
Table 1. input Current Limit Setting from PSEL
PSEL Pin
High
Low
inPUT CURRENT LIMIT
(ILIM)
500 mA
2.4A
VBUS_STAT
001
011
8.4.3.4 input Voltage Limit Threshold Setting (VINDPM Threshold)
The device supports wide range of input voltage limit (3.9 V – 5.4V) for USB. The default VINDPM setting is
4.5V.
In addition to absolute VINDPM voltage setting, the device supports dynamic VINDPM settings which tracks the
battery voltage. This function can be enabled via the VDPM_BAT_TRACK[1:0] register bits. When enabled, the
actual input voltage limit will be the higher of the VINDPM register and VBAT + VDPM_BAT_TRACK offset.
8.4.3.5 Converter Power-Up
After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery
charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.
The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input
current limit is d to the lower of 200 mA or IINDPM register setting. After the system rises above 2.2 V, the
device limits input current to the value of IINDPM register.
As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed
frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery
voltage, charge current and temperature, simplifying output filter design.
A type III compensation network allows using ceramic capacitors at the output of the converter. An internal
sawtooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp
height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage.
in order to improve light-load efficiency, the device switches to PFM control at light load when battery is below
minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is
set by the voltage ratio of SYS and VBUS. The PFM_DIS bit can be used to prevent PFM operation in either
buck or boost configuration.
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