CP3SP33 Datasheet, PDF (383/407 Pages) National Semiconductor (TI) – CP3SP33 Connectivity Processor with Cache, DSP, and Bluetooth, USB, and Dual CAN Interfaces

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36.11 Microwire/SPI Timing
Table 36-6. Microwire/SPI Timing
DESCRIPTION ⁽¹⁾
MICROWIRE/SPI INPUT SIGNALS
t_MSKh Microwire Clock High
t_MSKl Microwire Clock Low
t_MSKp Microwire Clock Period
t_MSKh MSKn Hold (slave only)
t_MSKs MSKn Setup (slave only)
t_{MWCS MWCSn Hold (slave only)}
h
t_{MWCS MWCSn Setup (slave only)}
s
t_MDIh
Microwire Data In Hold (master)
Microwire Data In Hold (slave)
t_MDIs Microwire Data In Setup
MICROWIRE/SPI OUTPUT SIGNALS
t_MSKh Microwire Clock High
t_MSKl Microwire Clock Low
t_MSKp Microwire Clock Period
t_MSKd MSKn Leading Edge Delayed (master only)
t_MDOf Microwire Data Float (slave only)
t_MDOh Microwire Data Out Hold
t_MDOnf Microwire Data No Float (slave only)
t_MDOv Microwire Data Out Valid
t_MITOp MDODIn to MDIDOn (slave only)
(1) Specified by design.
REFERENCE
At 2.0V (both edges), See Figure 36-13
At 0.8V (both edges), See Figure 36-13
SCIDL bit = 0; Rising Edge (RE) MSKn to next RE MSKn, See
Figure 36-13
SCIDL bit = 1; Falling Edge (FE) MSKn to next FE MSKn, See
Figure 36-14
After MWCSn goes inactive, See Figure 36-13
Before MWCSn goes active, See Figure 36-13
SCIDL bit = 0: After FE MSKn, See Figure 36-13
SCIDL bit = 1: After RE MSKn, See Figure 36-14
SCIDL bit = 0: Before RE MSKn, See Figure 36-13
SCIDL bit = 1: Before FE MSKn, See Figure 36-14
Normal Mode: After RE MSKn, See Figure 36-13
Alternate Mode: After FE MSKn, See Figure 36-15
Normal Mode: After RE MSKn, See Figure 36-13
Alternate Mode: After FE MSKn, See Figure 36-15
Normal Mode: Before RE MSKn, See Figure 36-13
Alternate Mode: Before FE MSKn, See Figure 36-15
At 2.0 V (both edges), See Figure 36-13
At 0.8 V (both edges), See Figure 36-13
SCIDL bit = 0: Rising Edge (RE) MSKn to next RE MSKn, See
Figure 36-13
SCIDL bit = 1: Falling Edge (FE) MSKn to next FE MSKn, See
Figure 36-14
Data Out Bit 7 Valid, See Figure 36-13
After RE on MWCSn, See Figure 36-13
Normal Mode: After FE MSKn, See Figure 36-13
Alternate Mode: After RE MSKn, SeeFigure 36-14
After FE on MWCSn, See Figure 36-14
Normal Mode: After FE on MSKn, See Figure 36-13
Alternate Mode: After RE on MSKn, See Figure 36-13
Propagation Time Value is the same in all clocking modes of the
Microwire, See Figure 36-17
CP3SP33
SNOSCW5 – MAY 2013
MIN
MAX UNIT
80
ns
80
ns
200
ns
200
40
ns
80
ns
40
ns
40
80
ns
80
0
ns
0
40
ns
40
80
ns
80
40
ns
40
ns
ns
100
0.5 t_MSK
1.5 t_MSK ns
25 ns
ns
0
0
25 ns
ns
25
25 ns
Copyright © 2013, Texas Instruments Incorporated
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Electrical Specifications 383