CP3SP33 Datasheet, PDF (272/407 Pages) National Semiconductor (TI) – CP3SP33 Connectivity Processor with Cache, DSP, and Bluetooth, USB, and Dual CAN Interfaces

CP3SP33
SNOSCW5 – MAY 2013
www.ti.com
The format shown in Figure 27-6 consists of one start bit, nine data bits, and one or two stop bits. This
format also supports the UART attention feature. When operating in this format, all eight bits of UnTBUF
and UnRBUF are used for data. The ninth data bit is transmitted and received using two bits in the control
registers, called UXB9 and URB9. Parity is not generated or verified in this mode.
3
Start
Bit
9-Bit Data
1S
Start
3a
Bit
9-Bit Data
2S
DS065
Figure 27-6. . 9-bit Data Frame Options
27.2.6 Baud Rate Generator
The Baud Rate Generator creates the basic baud clock from the PCLK Clock. The PCLK Clock is passed
through a two-stage divider chain consisting of a 5-bit baud rate prescaler (UnPSC) and an 11-bit baud
rate divisor (UnDIV).
The relationship between the 5-bit prescaler select (UnPSC) setting and the prescaler factors is shown in
Table 27-1.
PRESCALER
SELECT
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
Table 27-1. Prescaler Factors
PRESCALER FACTOR
No clock
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
PRESCALER SELECT
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
PRESCALER FACTOR
8.5
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
16
A prescaler factor of zero corresponds to “no clock.” The “no clock” condition is the UART power down
mode, in which the UART clock is turned off to reduce power consumption. Software must select the “no
clock” condition before entering a new baud rate. Otherwise, it could cause incorrect data to be received
or transmitted. The UnPSR register must contain a value other than zero when an external clock is used
at CKX.
272 Dual/Quad UART
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