CP3SP33 Datasheet, PDF (141/407 Pages) National Semiconductor (TI) – CP3SP33 Connectivity Processor with Cache, DSP, and Bluetooth, USB, and Dual CAN Interfaces

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CP3SP33
SNOSCW5 – MAY 2013
ADC2UP
DACUP
ADC1DOWN
ADC2DOWN
DACDOWN
ZXDL
ZXDR
MICCLP
STCLP
The ADC2 Power-Up bit enables an interrupt when ADC2 has powered up.
0 – ADC2 power-up interrupt disabled.
1 – ADC2 power-up interrupt enabled.
The DAC Power-Up bit enables an interrupt when the stereo DAC has powered up.
0 – DAC power-up interrupt disabled.
1 – DAC power-up interrupt enabled.
The ADC1 Power-Down bit enables an interrupt when ADC1 has powered down.
0 – ADC1 power-down interrupt disabled.
1 – ADC1 power-down interrupt enabled.
The ADC2 Power-Down bit enables an interrupt when ADC2 has powered down.
0 – ADC2 power-down interrupt disabled.
1 – ADC2 power-down interrupt enabled.
The DAC Power-Down bit enables an interrupt when the DAC has powered down.
0 – DAC power-down interrupt disabled.
1 – DAC power-down interrupt enabled.
The Zero-Crossing Detector Left Channel bit enables an interrupt when the left-channel
reconstruction filter output crosses zero. This is useful if the gain of an external audio
device is to be changed. Internal gains are controlled automatically on these events.
0 – Zero-crossing interrupt disabled.
1 – Zero-crossing interrupt enabled.
The Zero-Crossing Detector Right Channel bit enables an interrupt when the right-
channel reconstruction filter output crosses zero.
0 – Zero-crossing interrupt disabled.
1 – Zero-crossing interrupt enabled.
The Microphone Clipping bit enables an interrupt when the DIGMIC1 input gain stage
clips.
0 – Microphone clipping interrupt disabled.
1 – Microphone clipping interrupt enabled.
The Sidetone Clipping bit enables an interrupt when either sidetone feed to the DACs
clip.
0 – Sidetone clipping interrupt disabled.
1 – Sidetone clipping interrupt enabled.
20.10.10 Codec Interrupt Pending/Clear Register (TCDCIRQPNDCLR)
The TCDCIRQPNDCLR register is a 16-bit, read/write register that indicates the state of pending interrupt
requests. The bits in this register correspond to the interrupt enable bits in the TCDCIRQEN register. A set
bit in the TCDCIRQPNDCLR register indicates that the request is enabled and asserted. The
TCDCIRQPNDCLR register is also used by the interrupt service routine to clear these requests. Writing 1
to a bit in this register clears the request. Writing 0 has no effect. After reset, this register is cleared to
0000h.
7
ADC1DOWN
6
DACUP
15
Reserved
5
ADC2UP
4
ADC1UP
14
13
STCLP
12
MICCLP
3
RGTFIFO
11
ZXDR
2
LFTFIFO
10
ZXDL
1
ADC2FIFO
9
DACDOWN
0
ADC1FIFO
8
ADC2DOWN
20.10.11 Codec Compensation Filter C0/4 Tap Register (TCDCCOMP0)
The TCDCCOMP0 register is a 16-bit, read/write register that specifies the C0 and C4 coefficients of the
compensation filter, when the CUSTCOMP bit of the TCDCDSP register is set. When the CUSTCOMP bit
is clear, the TCDCCOMP0 register is ignored. After reset, this register is cleared to 0000h
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