CP3SP33 Datasheet, PDF (1/407 Pages) National Semiconductor (TI) – CP3SP33 Connectivity Processor with Cache, DSP, and Bluetooth, USB, and Dual CAN Interfaces

CP3SP33
www.ti.com
SNOSCW5 – MAY 2013
Connectivity Processor with Cache, DSP, and Bluetooth®, USB, and Dual CAN Interfaces
Check for Samples: CP3SP33
1 Introduction
1.1 Features
123
• CPU Features
– Fully static RISC processor core, capable of
operating from 0 to 96 MHz with zero
wait/hold state
– Minimum 10.4 ns instruction cycle time with
a 96-MHz internal clock frequency, based on
a 12-MHz external input
– 4K-byte, 4-way set-associative instruction
cache
– 69 independently vectored peripheral
interrupts
• DSP Features
– Capable of operating up to 96 MHz
– 16-bit fixed-point arithmetic, dual-MAC
architecture
– 32-bit interface to 4K-byte RAM shared with
CPU
– 32-bit external bus interface
– Bus master interface to audio peripherals
and I/O
• Memory
– 4K bytes CPU instruction cache
– 32K bytes CPU data RAM
– 4K bytes CPU/DSP shared RAM
– 24K bytes DSP program RAM
– 24K bytes DSP data RAM
– 8K bytes Bluetooth^® sequencer and data
RAM
– Addresses up to 96M bytes (FBGA-224
package) or 8M bytes (FBGA-144 package) of
external memory
• Broad Range of Hardware Communications
Peripherals
– Bluetooth Lower Link Controller (LLC)
including a shared 7K byte Bluetooth data
RAM and 1K byte Bluetooth Sequencer RAM
– Universal Serial Bus (USB) 2.0 On-The-Go
– Audio/telematics codec with dual ADC
inputs and high quality stereo DAC output
– Two CAN interfaces with 15 message buffers
conforming to CAN specification 2.0B active
– Two ACCESS.bus serial bus interfaces (I²C
compatible)
– Two 8/16-bit SPI, Microwire/Plus serial
interfaces
– I²S digital audio bus interface
– Four Universal Asynchronous
Receiver/Transmitter (UART) channels, one
channel has USART capability
– Advanced Audio Interface (AAI) to connect
to external 8/ 13-bit PCM Codecs as well as
to ISDN-Controllers through the IOM-2
interface (slave only)
– Two CVSD/PCM converters, for supporting
two bidirectional audio connectionsM
• External Bus Interface Shared Between CPU
and DSP
– 16/32-bit data busbus interface
– 23-bit address bus
– 3 programmable chip select outputs
– Up to 96M bytes external memory
– 8-level write buffer
• General-Purpose Hardware Peripherals
– 10-channel, 10-bit A/D Converter (ADC)
– 16-channel DMA controller
– Dual 16-bit Multi-Function Timer (MFT)
– Dual Versatile Timer Units (VTU), each with
four independent timers
– Timing and Watchdog Unit
• Extensive Power and Clock Management
Support
– Two Phase Locked Loops (PLL) for
synthesizing independent system and audio
peripheral clocks
– Two independent oscillators for Active mode
(12 MHz) and Power Save mode (32.768 kHz)
clocks
– Low-power modes (Power Save, Idle, and
Halt) for slowing or stopping clocks to
optimize power consumption while meeting
application needs
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a registered trademark of Bluethooth SIG, Inc.
2
Teak is a registered trademark of ParthusCeva, Inc.
3
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated