CP3SP33 Datasheet, PDF (210/407 Pages) National Semiconductor (TI) – CP3SP33 Connectivity Processor with Cache, DSP, and Bluetooth, USB, and Dual CAN Interfaces

CP3SP33
SNOSCW5 – MAY 2013
www.ti.com
22.11.1 External Connection
The CAN module uses the CANnTX and CANnRX pins to connect to the physical layer of the CAN
interface. They provide the functionality described in Table 22-20.
Table 22-20. External CAN Pins
Signal Name
CANnTX
CANnRX
Type
Output
Input
Description
Transmit data to the CAN bus
Receive data from the CAN bus
The logic levels are configurable by the CTX and CRX bits of the Global Configuration Register CGCRn
(see Section 22.10.6).
22.11.2 Transceiver Connection
An external transceiver chip must be connected between the CAN block and the bus. It establishes a bus
connection in differential mode and provides the driver and protection requirements. Figure 22-31 shows a
possible ISO-High-Speed configuration.
120
Termination
APB Bus
CAN
Interface
CANnRX
CANnTX
Transceiver Chip
REF
RX
TX
RS
VCC
BUS_H
BUS_L
GND
VCC
CAN bus
signals
To other
modules
120
DS344
Figure 22-31. External Transceiver
22.11.3 Timing Requirements
Processing messages and updating message buffers require a certain number of clock cycles, as shown
in Table 22-21. These requirements may lead to some restrictions regarding the Bit Time Logic settings
and the overall CAN performance which are described below in more detail. Wait cycles need to be added
to the cycle count for CPU access to the object memory as described in Section 22.9.1. The number of
occurrences per frame is dependent on the number of matching identifiers.
Table 22-21. CAN Module Internal Timing
Task
Copy hidden buffer to receive message buffer
Update status from TX_RTR to TX_ONCE_RTR
Cycle Count
17
3
Occurrence/Frame
0–1
0–15
210 Dual CAN Interfaces
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