CP3SP33 Datasheet, PDF (106/407 Pages) National Semiconductor (TI) – CP3SP33 Connectivity Processor with Cache, DSP, and Bluetooth, USB, and Dual CAN Interfaces

CP3SP33
SNOSCW5 – MAY 2013
Table 17-2. Multi-Input Wake-Up Registers (continued)
NAME
WKICTL2
WKICTL3
WKICTL4
WKISTAT
ADDRESS
FF C074h
FF C078h
FF C07Ch
FF C090h
DESCRIPTION
Interrupt Control Register 2
Interrupt Control Register 3
Interrupt Control Register 4
Interrupt Status Register
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17.1.1 Rising Edge Pending Register n (WKRPNDn)
The WKRPNDn registers are 32-bit, read/write registers that indicate whether a rising edge has been
detected on the corresponding MIWU input. Bits 31:0 of WKRPND1 correspond to MIWU inputs 31:0 Bits
31:0 of WKRPND2 correspond to MIWU inputs 63:32. Writing 1 to bits in the WKCLRn registers clears the
corresponding bits in the WKRPNDn registers. The WKRPNDn registers are cleared at reset. The register
format is shown below.
31
0
WKRPD
WKRPD
The Wake-Up Rising Edge Pending bits indicate whether a rising edge has occurred on the
corresponding MIWU inputs since the bits were last cleared.
0 – No rising edge occurred.
1 – Rising edge occurred.
17.1.2 Falling Edge Pending Register n (WKFPNDn)
The WKFPNDn registers are 32-bit, read/write registers that indicate whether a falling edge has been
detected on the corresponding MIWU input. Bits 31:0 of WKFPND1 correspond to MIWU inputs 31:0 Bits
31:0 of WKFPND2 correspond to MIWU inputs 63:32. Writing 1 to bits in the WKCLRn registers clears the
corresponding bits in the WKFPNDn registers. The WKFPNDn registers are cleared at reset. The register
format is shown below.
31
0
WKFPD
WKFPD The Wake-Up Falling Edge Pending bits indicate whether a falling edge has occurred on the
corresponding MIWU inputs since the bits were last cleared.
0 – No falling edge occurred.
1 – Falling edge occurred.
17.1.3 Clear Pending Register n (WKCLRn)
The WKCLRn registers are 32-bit, write-only registers that clear bits in the WKRPNDn and WKFPNDn
registers. Writing 1 to a WKCLRn bit clears the corresponding bit in each of the other registers. WKCLR1
clears bits in WKRPND1 and WKFPND1, and WKCLR2 clears bits in WKRPND2 and WKFPND2. The
register format is shown below.
31
0
WKCL
106 Multi-Input Wake-Up
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