DRV401-Q1 Datasheet, PDF (33/39 Pages) Texas Instruments – DRV401-Q1 Sensor Signal Conditioning Device for Closed-Loop Magnetic Current Sensor

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DRV401-Q1
SBOS814 – DECEMBER 2016
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Thermal Pad
Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but
board layout greatly influences overall heat dissipation. Table 1 shows the thermal resistance (θ_JA) for the
package with the exposed thermal pad soldered to a normal PCB, as described in PowerPAD Thermally-
Enhanced Package (SLMA002). Refer to EIA/JEDEC Specifications JESD51-0 to 7, QFN/SON PCB Attachment
(SLUA271) and Quad Flatpack No-Lead Logic Packages (SCBA017). These documents are available for
download at www.ti.com.
Table 1. θ_JA and θ_JP Estimations According to EIA/JED51-7⁽¹⁾
PARAMETER
VQFN
θ_JP
9
θ_JA with still air
40
θ_JA with forced airflow (150 lfm)
38
(1) θ_JA = junction-to-ambient thermal resistance.
TI recommends measuring the temperature as close as possible to the thermal pad. The relatively low thermal
impedance, θ_JP, of less than 10°C/W (with some additional °C/W to the temperature test point on the PCB)
allows good estimation of the junction temperature in the application.
The thermal pad on the PCB must contain nine or more vias for the VQFN package.
Component population, layout of traces, layers, and air flow strongly influence heat dissipation. Worst-case load
conditions must be tested in the actual operating environment to ensure proper thermal conditions. Minimize
thermal stress for proper long-term operation with a junction temperature well below 125°C.
NOTE
All thermal models have an accuracy ≈ 20%.
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