DRV401-Q1 Datasheet, PDF (18/39 Pages) Texas Instruments – DRV401-Q1 Sensor Signal Conditioning Device for Closed-Loop Magnetic Current Sensor

DRV401-Q1
SBOS814 – DECEMBER 2016
www.ti.com
Feature Description (continued)
The transition from normal operation to overload happens slowly because the inherent sensor transformer
characteristics induce the initial primary current step, as shown in Figure 39. As the transformer-induced
secondary current starts to decay, the compensation feedback driver increases the output voltage to maintain the
sensor core flux compensation at zero.
1
I_COMP1
3
4
I_COMP2
V(1 W ´ I_PRIM/10)
Sensor: 4 x 100
R_SH = 10 W
Step Response
2 kHz In
V(Gain) = Low
2
V_OUT
Channel 1: 2 V/div
Channels 2 through 4: 500 mV/div
50 ms/div
A current pulse of 0 A to 18 A (channel 1) generates the two I_COMP signals (channel 3 and channel 4). Channel 2
shows the resulting output signal (V_OUT). This test uses the M4645-X030 sensor with no bandwidth limitation, and a
20-sample average.
Figure 39. Primary Current Step Response
When the system compensation loop reaches the driving limit, the rising magnetic flux causes one of the probe
pulse-width modulator (PWM) half-periods to become shorter. The minimum half-period of the probe oscillation is
limited by the internal timing to 280 ns, based on the properties of the VAC magnetic sensors. After three
consecutive cycles of the same half-period being shorter than 280 ns, the DRV401-Q1 device enters overload-
latch mode. The device stores the I_COMP driver output signal polarity and continues producing the skewed-duty
cycle PWM signal. This action prevents the loss of compensation signal polarity information during strong
overloads. In this case, both PWM half-periods are short and approximately equal, because the field probe stays
completely in one of the saturated regions.
The overload-latch condition is removed after the primary current goes low enough for the I_COMP driver to
compensate, and both half-periods of the probe driver oscillation become longer than 280 ns (the field probe
comes out of the saturated region).
Peak voltages and currents generate during normal operations and overload conditions. Both probe connection
pins are internally protected against coupled energy from the magnetic core. Wiring between probe and device
inputs must be short and guarded against interference, as shown in the Layout Guidelines section.
For reliable operation, error detection circuits monitor the probe operation:
1. If the probe driver comparator (CMP) output stays low longer than 32 μs, the ERROR flag asserts active, and
the compensation current (I_COMP) is set to zero.
2. If the probe driver period is less than 275 ns on three consecutive pulses, the ERROR flag asserts active.
See the Error Conditions section for more details.
7.3.2 PWM Processing
The PWM and PWM outputs represent the probe output signal as a differential PWM signal. The signal drives
external circuitry and is used for synchronous ripple reduction. The PWM signal from the probe excitation and
sense stage is internally connected to a high-performance, switched-capacitor integrator followed by an
integrating-differentiating filter. The filter converts the PWM signal into a filtered delta signal and prepares the
PWM signal to drive the analog compensation coil driver. The gain roll-off frequency of the filter stage provides
high dc gain and loop stability. If additional gain is added from external circuitry, the internal gain is reduced by 8
dB, which asserts the GAIN pin high, as shown in the External Compensation Coil Driver section.
18
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