TMS320DM6441_17 Datasheet, PDF (32/236 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6441
SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010
www.ti.com
SIGNAL
NAME
EM_A[15]/
GPIO16/
VLYNQ_TXD3
EM_A[14]/
GPIO17/
VLYNQ_RXD3
EM_A[13]/
GPIO18
EM_A[12]/
GPIO19
EM_A[11]/
GPIO20
EM_A[10]/
GPIO21
EM_A[9]/
GPIO22
EM_A[8]/
GPIO23
EM_A[7]/
GPIO24
EM_A[6]/
GPIO25
EM_A[5]/
GPIO26
EM_A[4]/
GPIO27
EM_A[3]/
GPIO28
EM_A[2]/
(CLE)/
HCNTL0
EM_A[1]/
(ALE)/
HHWIL
EM_A[0]/
DA2/
HCNTL1/
GPIO53
Table 2-9. EMIFA Terminal Functions (continued)
TYPE ⁽¹⁾ OTHER^{(2) (3)}
NO.
DESCRIPTION
P3 I/O/Z
DV_DD18
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 15 output EM_A[15].
P4 I/O/Z
N4 I/O/Z
R1 I/O/Z
P2 I/O/Z
P1 I/O/Z
M4 I/O/Z
N3 I/O/Z
N2 I/O/Z
N1 I/O/Z
K3 I/O/Z
K4 I/O/Z
K2 I/O/Z
J1 I/O/Z
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 14 output EM_A[14].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 13 output EM_A[13].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 12 output EM_A[12].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 11 output EM_A[11].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 10 output EM_A[10].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 9 output EM_A[9].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 8 output EM_A[8].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 7 output EM_A[7].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 6 output EM_A[6].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 5 output EM_A[5].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 4 output EM_A[4].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 3 output EM_A[3].
This pin is multiplexed between EMIFA and HPI.
For EMIFA, this pin is the EM_A[2] address line.
J2 I/O/Z
J4 I/O/Z
DV_DD18
DV_DD18
This pin is multiplexed between EMIFA (NAND/SmartMedia.xD) and HPI.
This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO.
For EMIFA, this is Address output EM_A[0], which is the least significant bit on a
32-bit word address.
When connected to a 16-bit asynchronous memory, this pin is the 2nd bit of the
address.
For an 8-bit asynchronous memory, this pin is the 3rd bit of the address.
32
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