TMS320DM6441_17 Datasheet, PDF (109/236 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6441
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SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010
6.6 Clock PLLs
There are two independently controlled PLLs on DM6441. PLL1 generates the frequencies required for the
DSP, ARM, VICP, DMA, VPFE, and other peripherals. PLL2 generates the frequencies required for the
DDR2 interface and the VPBE in certain modes. The recommended reference clock for both PLLs is the
27-MHz crystal input. The USB2.0 PHY contains a third PLL embedded within it and the 24-MHz oscillator
is its reference clock source. This particular PLL is only usable for USB operation, and is discussed further
in the TMS320DM644x DMSoC Universal Serial Bus (USB) Controller User's Guide (literature number
SPRUE35). See also the TMS320DM644x DMSoC Peripherals Overview Reference Guide (literature
number SPRUE19).
A summary of the PLL controller registers is shown in Table 6-12. For more details, see the
TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).
Table 6-12. PLL and Reset Controller Registers Memory Map
HEX ADDRESS RANGE
0x01C4 0800
0x01C4 08E4
0x01C4 0900
0x01C4 0910
0x01C4 0918
0x01C4 091C
0x01C4 0920
0x01C4 0928
0x01C4 092C
0x01C4 0938
0x01C4 093C
0x01C4 0940
0x01C4 0944
0x01C4 0948
0x01C4 094C
0x01C4 0950
0x01C4 0960
0x01C4 0964
0x01C4 0C00
0x01C4 0D00
0x01C4 0D10
0x01C4 0D18
0x01C4 0D1C
0x01C4 0D20 - 0x01C4 0D2B
0x01C4 0D2C
0x01C4 0D38
0x01C4 0D3C
0x01C4 0D40
0x01C4 0D44
0x01C4 0D48
0x01C4 0D4C
REGISTER ACRONYM
DESCRIPTION
PLL1 Controller Registers
PID
Peripheral Identification and Revision Information Register
RSTYPE
Reset Type Register
PLLCTL
PLL Controller 1 Operations Control Register
PLLM
PLL Controller 1 Multiplier Control Register
PLLDIV1
PLL Controller 1 Control-Divider 1 Register (SYSCLK1)
PLLDIV2
PLL Controller 1 Control-Divider 2 Register (SYSCLK2)
PLLDIV3
PLL Controller 1 Control-Divider 3 Register (SYSCLK3)
POSTDIV
PLL Controller 1 Post-Divider Control Register
BPDIV
PLL Controller 1 Bypass Control-Divider Register (SYSCLKBP)
PLLCMD
PLL Controller 1 Command Register
PLLSTAT
PLL Controller 1 Status Register (Shows PLLCTRL Status)
ALNCTL
PLL Controller 1 Alignment Control Register
(Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation)
DCHANGE
PLL Controller 1 Divider Change Register
(Indicates if SYSCLK Divide Ratio has Been Modified)
CKEN
PLL Controller 1 Clock Enable Register
CKSTAT
PLL Controller 1 Clock Status Register (For All Clocks Except SYSCLKx)
SYSTAT
PLL Controller 1 System Clock Status 1 Register (Indicates SYSCLK on/off
Status)
PLLDIV4
PLL Controller 1 Control-Divider 4 Register (SYSCLK4)
PLLDIV5
PLL Controller 1 Control-Divider 5 Register (SYSCLK5)
PID
Peripheral Identification and Revision Information Register
PLLCTL
PLL Controller 2 Operations Control Register
PLLM
PLL Controller 2 Multiplier Control Register
PLLDIV1
PLL Controller 2 Control-Divider 1 Register (SYSCLK1)
PLLDIV2
PLL Controller 2 Control-Divider 2 Register (SYSCLK2)
POSTDIV
PLL Controller 2 Post-Divider Control Register
BPDIV
PLL Controller 2 Bypass Control-Divider Register (SYSCLKBP)
PLLCMD
PLL Controller 2 Command Register
PLLSTAT
PLL Controller 2 Status Register (Shows PLLCTRL Status)
ALNCTL
PLL Controller 2 Alignment Control Register
(Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation)
DCHANGE
PLL Controller 2 Divider Change Register
(Indicates if SYSCLK Divide Ratio has Been Modified)
CKEN
PLL Controller 2 Clock Enable Register
CKSTAT
PLL Controller 2 Clock Status Register (For All Clocks Except SYSCLKx)
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Peripheral and Electrical Specifications 109
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